art in VLSI design

The state of the art in VLSI design: layouts, circuits, logic, floorplanning, and architectures
New techniques for maximizing performance and minimizing power usage
Extensive new coverage of advanced interconnect models, including copper
Up-to-the-minute coverage of IP-based design
Detailed HDL introductions: Verilog and VHDL
The #1 VLSI design guide-now fully updated to reflect the latest advances in SoC design

Modern VLSI Design, System-on-Chip Design, Third Edition is a comprehensive, "bottom-up" guide to the entire VLSI design process, focusing on the latest solutions for System-on-Chip (SoC) design. Wayne Wolf reviews every aspect of digital design, from planning and layout to fabrication and packaging, introducing today's most advanced techniques for maximizing performance, minimizing power utilization, and achieving rapid design turnarounds. Coverage includes:

Advanced interconnect models: new techniques for overcoming delay bottlenecks, reducing crosstalk, and modeling copper interconnect
Advanced low-power design techniques for enhancing reliability and extending battery life in portable consumer electronics
Testing solutions for every level of abstraction, from circuits to architecture
Practical IP-based design solutions
A thorough overview of HDLs, including new introductions to Verilog and VHDL
Techniques for improving testability, embedded processors, and more
VLSI design for today's high-performance, low-power devices requires broader, deeper skills than ever before. Modern VLSI Design, System-on-Chipbrings together those skills in a single, comprehensive resource that will be invaluable to every VLSI design engineer and manager.

Table of Contents


1: Digital Systems and VLSI.
Why Design Integrated Circuits?
Integrated Circuit Manufacturing.
CMOS Technology.
Integrated Circuit Design Techniques.
A Look into the Future. Summary.

2: Transistors and Layout.
Fabrication Processes.
Transistors.
Wires and Vias.
Design Rules.
Layout Design and Tools.

3: Logic Gates.
Combinational Logic Functions.
Static Complementary Gates.
Switch Logic.
Alternative Gate Circuits.
Wires and Delay.

4: Combinational Logic Networks.
Layout Design Methods.
Simulation.
Combinational Network Delay.
Crosstalk.
Power Optimization.
Switch Logic Networks.
Combinational Logic Testing.

5: Sequential Machines.
Latches and Flip-Flops.
Sequential Systems and Clocking Disciplines.
Sequential System Design.
Power Optimization.
Design Validation.
Sequential Testing.

6: Subsystem Design.
Subsystem Design Principles.
Combinational Shifters.
Adders.
ALUs.
Multipliers.
High-Density Memory.
Field-Programmable Gate Arrays.
Programmable Logic Arrays.

7: Floorplanning.
Floorplanning Methods.
Floorplanning Large Chips.
Off-Chip Connections.

8: Architecture Design.
Hardware Description Languages.
Register-Transfer Design.
High-Level Synthesis.
Architecture for Low Power.
Architecture Testing.

9: Chip Design.
Design Methodologies.
Kitchen Timer Chip.
PDP-8 Data Path.

10: CAD Systems and Algorithms.
CAD Systems.
Simulation.
Layout Synthesis.
Layout Analysis.
Timing Analysis and Optimization.
Logic Synthesis.
Test Generation.
Sequential Machine Optimizations.
Scheduling and Binding.
Hardware/Software Co-Design.

Appendix A: A Chip Designer's Lexicon.

Appendix B: Chip Design Projects.
Class Project Ideas. Project Proposal and Specification. Design Plan. Design Checkpoints and Documentation.

Appendix C: Design Modeling.
Hardware Modeling in VHDL.
Hardware Modeling in C.