Analog circuit simulators

This paper presents a model for characterizing delay in semicustom CMOS logic cells
that accounts for input slew rate and output capacitance loading. The logic cells are
decomposed into branches of series connected transistors. A method for deriving the
model parameters and VHDL modeling of the branches is presented. This method
drastically reduces the number of model parameters required for delay characterization.
1 Introduction
Analog circuit simulators suer from severe memory and execution time constraints and are
hence unsuitable for VLSI circuits. Logic and timing simulators are much faster, but their
accuracy depends upon the accuracy of the model for cell delay. In order to obtain a good
accuracy, the dependence of CMOS cell delay upon both input slope (IS) and output load
must be taken into account. A input slope dependent timing model for characterizing delay
in CMOS logic gates was presented by Mishelo in [1]. In order to reduce the number of
parameters for delay characterization, we decompose the CMOS cells into branches of series
connected transistors, and characterize the branches rather the entire cell. The concept of
branch-modeling schematics is detailed in [2]. The main advantage is the construction of
simulation models for the cells. As each cell is constructed with branches, it is possible to
describe a model for each dierent branch to obtain the corresponding model of the complete
cell. The number of models to develop is therefore drastically reduced and simplied: the
dierent branches present 1, 2 or 3 transistors in series, for both n-branch and p-branch
networks [2]. The very long work of designing dedicated models for each cell is therefore
avoided.
Our characterization is based on piece-wise linear tting of the delay model parameters to
a number of Spice3 simulations. The model parameters for each branch are derived from
Spice simulations of the netlist based on cell's layout using lateral interconnect capacitance.
Level-3 transistor model is used. The number of transistors in series has been limited to 3
for both n- and p-branch type.