Accellera Designer's Forum

Accellera

* Accellera Designer's Forum
* Open Verification Library
(formerly OVI Assertion) (see also OpenVerification.org)
* Other:
o C/C++ Class Library Standardization Working Group (alc-cwg)
o Interface Technical Committee (itc)
o Open Kit (openkit) Technical Committee
* System Level Design:
o Language (slds, sldl ) Study Group
(also former OVI Architecture Language Committee)
o Core Working Group (slds-cwg )
o Rosetta Working Group (slds-rosetta)
o Semantics Working Group (slds-semantics )
* SystemVerilog :
o 3.0 LRM
o 3.1 LRM
o Basic and Design Committee
o Testbench and Enhancements
o C Interface
o Assertion
* Verilog:
o Verilog Analog Mixed-Signal (verilog-ams) Working Group
o Verilog Formal Verification (vfv) Working Group
* VHDL:
o (VHDL) Design Constraints Working Group (dcwg)
o VIUF Proceedings
o VHDL Users' Group / VIUF are now Accellera Designers Forum.

HDL Open Source Models, etc.

* Free VHDL models from Free Model Foundry (FMF)
* Free VHDL core models from OpenCores
* comp.lang.vhdl FAQ and
* Misc. submissions (from VUG/VIUF meetings, etc.)
* VHDL models, info, etc. from RASSP E&F
(especially RASSP RTWG Taxonomy on VHDL Models and Terminology))

GPL / Open Source EDA / HDL Tools

* Synopsys Inc. open source OpenMAST Language and Tools
* FreeHDL VHDL compiler / simulator
* GPL EDA tools
* Mentor Graphics Corporation free VHDL-AMS tools
* OpenCollector tools / models list
* OpenEDA tools
* SAVANT VHDL tools from University of Cincinnati
* VAUL VHDL tools from Univ of Dortmund EE(English text)
* White Peak Technologies free VHDL tools

Other EDA / CAD Groups

* ESTS: Expert Services & Tools for Semiconductors Trade Association
* Semiconductor Research Corporation and the MARCO Focus Center Research Program
(see especially GSRC, IFC, and CSS)
* ACM Special Interest Group on Design Automation (SIGDA)
* Advanced EDA Benchmark Datasets Effort (SRC/IEEE-CAS/SIGDA) (benchmrk)
* EDA Companies (EDAC)
* EDA Standards Industry Council (EDA Stds IC)
* Glossary of Standards at SI2 (old CFI)
* IEC TC93- USA TAG Activity (mirror)
* IEC TC93 Working Group 1: Interoperability (mirror)
* IEEE Circuits and Systems Society
Computer-Aided Network Design (CANDE)
* IEEE Computer Society
Design Automation Technical Committee (DATC)
* ISO TC184: Design Automation:
o Std 10303-210 Electronic Assembly, Interconnect and Packaging Design
o Std 10303 - Standard Exchange of Product Data STEP
(ISO TC184/SC4/WG4)
o Std 13584 - Part Libraries STEP Application
(ISO TC184/SC4/WG2)
* Int. Society for Hybrid Microcircuits (ISHM)
* The Institute for Interconnecting and Packaging Electronic Circuits ( IPC)
* NCSU CAD Benchmarking Library




IEEE Design Automation Standards Committee (DASC)

* P1076 Standard VHDL Language Reference Manual (VASG)
o VHDL-200x: the next revision
o Issues Screening and Analysis Committee (ISAC)
o VHDL Programming Language Interface Task Force (VHPI)
* P1076.1 Standard VHDL Analog and Mixed-Signal Extensions (VHDL-AMS)
* P1076.1.1 Standard VHDL Analog and Mixed-Signal Extensions - Packages for Multiple Energy Domain Support (StdPkgs)
* P1076.4 Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification (VITAL)
* P1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis (SIWG)
* P1364.1 Standard for Verilog Register Transfer Level Synthesis (VLOG-Synth)
* P1481 Standard for Integrated Circuit (IC) Open Library Architecture (OLA) (IEEE1481R)
* P1499 Standard Interface for Hardware Description Models of Electronic Components (OMF)
* P1603 Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks (ALF)
* P1647 Standard for the Functional Verification Language 'e' (eWG)
* P1666 Standard System C Language Reference Manual (systemc) [cosponsored with IEEE-SA CAG]
* P1685 SPIRIT XML Standard for IP Description (IEEE-1685)
* P1735 Design Intellectual Property (IP) Encryption and Rights Management. (IEEE-1735)
* SystemVerilog Working Group
o P1800 SystemVerilog: Unified Hardware Design, Specification and Verification Language (SV-IEEE1800) [cosponsored with IEEE-SA CAG]
o P1364 Standard for Verilog Hardware Description Language (IEEEVerilog)
* P1850 Standard for PSL: Property Specification Language (IEEE-1850) [cosponsored with IEEE-SA CAG]

Government Electronics and Information Technology Association (GEIA)

a sector of the Electronics Industries Alliance (EIA),
formerly the EIA Electronic Information Group - (EIG)

* Compact Modeling Council (CMC)
* I/O Buffer Information Specification (IBIS): ANSI/EIA-656
(see also IBIS)
* Rule Augmented Interconnect Layout (RAIL)
* Computer Aided Software Engineering (CASE)
* Electronic Data Interchange Format (EDIF) (The www.edif.org link is no longer valid.)

The Virtual Library EE page is a good source of links to other electrical engineering design resources.
EDA Industry Standing Conferences

* HDL Conference (HDLCON)
* International Forum on Design Languages ( FDL))
* Design Automation Conference (DAC)
* Design Automation & Test in Europe (DATE)
* Asian & Pacific Design Automation Conference (ASPDAC)
* IC CAD (ICCAD)
* International Symposium on Physical Design (ISPD)
* DesignCON (DesignCON)

Books

* Books listed in the FAQ for the newsgroup comp.lang.vhdl
* Amazon.com listings for VHDL, Verilog, and EDA





Copyright (c) 1994-2006 by Accellera, last edited: 06/14/06 at 1:40 PDT