Cmos fabrication patent info.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates generally to integrated circuit design and, more particularly, to a process for defining complementary metal oxide semiconductor ("CMOS") transistors.

[0003] 2. Description of the Related Art

[0004] Integrated circuits are typically produced according to a series of complex fabrication steps including deposition, masking, etching and doping steps. The complexity of the fabrication greatly increases the cost of the integrated circuits, and often results in relatively low manufacturing efficiency.

[0005] For example, for memory circuits or devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs) and ferroelectric (FE) memories, the fabrication of the CMOS logic around the periphery traditionally comprises a number of relatively time-consuming and expensive masking steps.

[0006] First, a mask is used to define the active areas of the transistors in the CMOS by shallow trench isolation (STI). According to some manufacturing methods, this same masking stage may be used to simultaneously define active areas in the array by STI. Next, a gate oxide is defined, typically in both the periphery and array. Using one mask for the n-channel metal oxide semiconductors (NMOS) and another mask for the p-channel metal oxide semiconductors (pMOS), the well, n-channel enhancement implants and polysilicon workfunction implants are defined in the next step.

[0007] The polysilicon for forming the gates in the CMOS may then be formed using another mask. The lightly doped drain (LDD) implant and Halo implant (or pocket implant, as it is sometimes referred to) may then be formed around the CMOS gates using one mask for the NMOS, one mask for the pMOS, and yet another mask for the array.

[0008] Spacers are then typically formed along the vertical sidewalls of gate electrodes of both the periphery and array. The source and drain regions for the transistors may then be doped using a mask for each of the nMOS and pMOS regions. Finally, a low k gap fill oxide is deposited along the top of the memory device, and the device undergoes rapid thermal processing (RTP) for dopant activation. The transistors and other circuit elements of the array and periphery are thereby defined, and lines may then be connected thereto according to other steps well known to those of skill in the art.

[0009] As is clear from the description above, a typical CMOS fabrication process necessitates the use of many masks, and is a complex, time-consuming process. An exemplary CMOS fabrication process flow as described above, for example, employs eight (8) masks from definition of field isolation until transistor source/drain doping for each of the NMOS and pMOS regions. There is a need, therefore, for a less complex manufacturing technique that would use fewer masks, and that would also have an improved yield in comparison to traditional techniques.

SUMMARY OF THE INVENTION

[0010] According to one aspect of the invention, a process is provided for forming a memory device. The method includes patterning gates in NMOS and pMOS regions for CMOS circuits. The pMOS regions are masked with a first mask. Source/drain doping and supplemental doping between source/drain regions and the gates are conducted in the nMOS regions while the pMOS regions remain masked with the first mask. The nMOS regions are masked with a second mask. Source/drain doping and supplemental doping between source drain regions and the gates are conducted in the pMOS regions while the NMOS regions remain masked with the second mask. Exemplary supplemental doping includes lightly doped drain (LDD) and pocket or Halo implants.

[0011] According to another aspect of the invention, a method of manufacturing a memory device is disclosed. The method includes providing a substrate and defining a pMOS region and an nMOS region in the substrate. A first gate is defined in the NMOS region, and a second gate is defined in the pMOS region. First and second spacers are formed over the first and second gates, respectively. The nMOS and pMOS regions are selectively masked, and at least a portion of the first spacers is etched back from the first gate while the pMOS region is masked.

[0012] According to another aspect of the invention, a method is provided for manufacturing a memory device. The method includes providing a substrate and defining at least two active areas within the substrate, where at least one of said active areas comprises an NMOS region, and at least another of said active areas comprising a pMOS region. A first gate is patterned within the NMOS region and a second gate is patterned within the pMOS region. First disposable spacers are formed on the first gate and second disposable spacers are simultaneously formed on the second gate. The first disposable spacers are trimmed to be smaller than a width of the second disposable spacer.

[0013] According to another aspect of the invention, a method of fabricating CMOS circuits includes defining field isolation, patterning CMOS gates and conducting complete CMOS transistor doping using six or fewer masks.

[0014] According to another aspect of the invention, an integrated circuit is provided. The integrated circuit comprises a substrate, an NMOS gate over an n-channel in the substrate, and a pMOS gate over a p-channel in the substrate. The nMOS and pMOS gates have approximately the same widths while the n-channel is shorter than the pMOS channel.

[0015] According to another embodiment of the invention, a system comprising a CMOS circuit is provided. The CMOS circuit comprises a substrate and a CMOS transistor gate formed integrally with the substrate. Source/drain regions are formed within the substrate near the gate, and lightly doped drain (LDD) regions are formed at least partially between the source/drain regions and the gate. A gap-fill oxide, with a dielectric constant of less than about 3.5 directly contacts sidewalls of the gate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] These and other aspects of the invention will be better understood from the detailed description of the preferred embodiments and from the appended drawings, which are meant to illustrate and not to limit the invention, and in which:

[0017] FIG. 1 is a flow chart illustrating one process for fabricating CMOS circuits according to a preferred embodiment of the present invention.

[0018] FIG. 2 illustrates a cross-sectional view of a portion of a memory device within which NMOS and pMOS transistors may be formed according to a preferred embodiment of the present invention.

[0019] FIG. 3 illustrates a cross-sectional view of the device of FIG. 2 after a mask step, optional spacer trim in n-channel areas, n+ implant and n-channel enhancements implant.

[0020] FIG. 4 illustrates a cross-sectional view of the device of FIG. 3 after spacer removal in n-channel areas, LDD implant and Halo implant.

[0021] FIG. 5 illustrates a schematic cross-sectional view of the NMOS region of the device of FIG. 4 after LDD implant and Halo implant.

Continue reading...
Full patent description for Cmos fabrication

Brief Patent Description - Full Patent Description - Patent Application Claims
Click on the above for other options relating to this Cmos fabrication patent application.
###
monitor keywords

How KEYWORD MONITOR works... a FREE service from FreshPatents
1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored.
3. Each week you receive an email with patent applications related to your keywords.
Start now! - Receive info on patent apps like Cmos fabrication or other areas of interest.
###


Previous Patent Application:
Cmos fabrication
Next Patent Application:
Method of forming an interlayer dielectric
Industry Class:
Semiconductor device manufacturing: process

###

Design/code © 2008 FreshContext LLC/Freshpatents.com. Website Terms and Conditions - Also read: About this Page
Patent data source: patents published by the United States Patent and Trademark Office (USPTO)
Information published here is for research/educational purposes only (and in conjunction with our Keyword Monitor) and is not meant to be used in place of the full USPTO patent document/images or a comprehensive patent archive search. Complete official applications are on file at the USPTO and often contain additional data/images (Freshpatents is currently text-only). FreshPatents.com is not affiliated with or endorsed by the USPTO or firms/individuals or products/designs/ideas related to listed patents.
FreshPatents.com Support
Thank you for viewing the Cmos fabrication patent info.
IP-related news and info