eInfochips

Design



From specification to first time right silicon; our expertise in architectures, methodology and design enables you to meet enhanced performance requirements and hasten time-to-market. We help you realize your product into highly integrated ASIC and SoC systems while reducing cost and skillfully leveraging our IP development and Integration skills.

eInfochips’ engineering team has taped out in excess of 130+ Chip ASIC/SoC designs with varied levels of complexity and integration. Several ASIC designs were implemented on 90 nm technology node with gate counts going up to 100 million and clock domains running up to 700 MHz. eInfochips has developed Cadence, Mentor, Synopsys, and Magma design flows, all of which have been deployed successfully to reach close to 100% first-pass silicon success.

Our offerings in this area include:

* Concept & Feasibility Study
* Technology Assessment
* Architecture Definition
* Micro Architecture Definition
* Design Partitioning
* RTL Modeling
* IP Integration
* Synthesis
* STA & DFT
* Design-for-Test support
* Basic software setup / Alpha testing
* Hardware/Software co-verification
* Foundry selection

Tools Expertise:

* Simulation tools: NC Sim, Modelsim, Questa, VCS
* Synthesis tools : Magma Blast Create, (Synopsys) Design Compiler
* S T A : PrimeTime(Synopsys). Magma .
* DFT : FastScan, DFT Advisor, MBistArchitect (all from Mentor Graphics)
* Physical Design : Magma – Blast Fusion; Cadence SoCEncounter

Domain Expertise:

* Networking
* Communications
* Bus based bridges
* Consumer
* Video

Our focus on customer requirements results in high levels of integration on a single chip and a significant reduction in technical risk.