cmos advantages

Title:
Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection
Document Type and Number:
United States Patent 6521952

Abstract:
An NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR) SOI-NSCR includes a P-type well and an N-type well. A first P+ doping region and a first N+ doping region are in the N-type well and form the anode of the SOI-NSCR. A second P+ doping region and a second N+ doping region are in the P-type well and form the cathode of the SOI-NSCR. The first P+ doping region, the N-type well, the P-type well and the second N+ doping region form a lateral SCR. A third N+ doping region is across the N-type well and the P-type well. A gate is in the P-type well, and the third N+ doping region, the gate and the second N+ doping region form an NMOS. A dummy gate is in the N-type well for isolating the first P+ doping region and the third N+ doping region. When a voltage is applied to the gate of the NMOS that turns on the NMOS, a forward bias is created from the N-type well to the P-type well that turns on the SOI-NSCR. When a voltage is applied to the third N+ doping region, a trigger current is generated that causes the lateral SCR to enter a latch state and so the SOI-NSCR is quickly turned on. Utilizing similar and related designs, the present invention discloses a PMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-PSCR), and ESD protection circuitry utilizing the SOI-NSCR and the SOI-PSCR.