Google Groups
asicdesign2vlsi
Visit this group
Google Groups
Subscribe to asicdesign2vlsi
Email:
Visit this group

Wednesday, October 29, 2008

Table of Contents

Table of Contents

Basic Stimulus Generation
Testbench Structure
Definition of Terms
Writing to Files
Reading from Files
More Reading from Files
The World of Perl
SRAM modeling
Passive SRAM Model
Signal Monitors
Generating Clock and Reset Stimulus
Approaches to Test Generation
File Read Method
VHDL pre-processing Method
Test-specific Entities
Configuration controlled Test Selection
Using Transaction Logs
Using Transaction Logs II
Using Behavioural Models
Recommended Directory Structure
Test Strategy
The End

No comments:

 
October (78)
  • Floorplanning Methods
  • Featured Case study
  • VLSI AND SYSTEM DESIGN
  • art in VLSI design
  • Chip-Level Thermal Simulator to Predict VLSI Chip ...
  • Floorplanning Methods
  • Featured Case study
  • VLSI AND SYSTEM DESIGN
  • art in VLSI design
  • Chip-Level Thermal Simulator to Predict VLSI Chip ...