Titre du document / Document title

Titre du document / Document title
Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models
Auteur(s) / Author(s)
SHAW Donald (1) ; AL-KHALILI Dhamin (2) ; ROZON Come (2) ;
Affiliation(s) du ou des auteurs / Author(s) Affiliation(s)
(1) Gennum Corporation, Burlington, Ont., L7R 3Y3, CANADA
(2) Department of Electrical and Computer Engineering, Royal Military College of Canada, P. O. Box 17000, Stn. Forces, Kingston, Ont., K7K 7B4, CANADA
Résumé / Abstract
This paper introduces a methodology for assessing the fault security attributes of Fault Secure (FS) circuits. Structural VHDL circuit descriptions are used to simulate the fault effects of realistic transistor level defects that occur in CMOS ICs. Defective standard cells are simulated at the analog level of ion and the resultant fault effects are implemented in defect-injectable VHDL models to allow logic simulation. Typical fault effects include functional changes, propagation delay increases, sequential logic faults, stuck-at faults, reduced noise margins, and increased IDDQ. The defect-injectable VHDL models are swapped into FS circuit designs and the effects of the defects are analyzed in the context of the digital circuit. The FS circuits can then be assigned a figure of merit based on the ratio of detected defects to those that actually cause output errors. To facilitate the execution of the methodology, an integrated software tool has been developed that, in combination with a commercial VHDL simulation tool, provides an automated means for determining the figure of merit. Implemented using a GUI, the new tool is user friendly and flexible enough to be used with various logic circuits and different IC technologies. Three different checker, as benchmarks, wére evaluated to demonstrate the FSA tool and the methodology to assess their relative fault security.
Revue / Journal Title
Integration ISSN 0167-9260 CODEN IVJODL
Source / Source
2002, vol. 32, no1-2, pp. 77-97 [21 page(s) (article)] (28 ref.)
Langue / Language
Anglais
Editeur / Publisher
Elsevier Science, Amsterdam, PAYS-BAS (1983) (Revue)
Mots-clés anglais / English Keywords
Integrated circuit ; Logic circuit ; Software tool ; Figure of merit ; Digital circuit ; Circuit design ; Noise reduction ; Logic simulation ; Logic model ; Complementary MOS technology ; Defect level ; Transistor ; VHDL language ; VLSI circuit ; CMOS integrated circuits ; Defect detection ;
Mots-clés français / French Keywords
Circuit intégré ; Circuit logique ; Outil logiciel ; Facteur mérite ; Circuit numérique ; Conception circuit ; Réduction bruit ; Simulation logique ; Modèle logique ; Technologie MOS complémentaire ; Niveau défaut ; Transistor ; Langage VHDL ; Circuit VLSI ; Circuit intégré CMOS ; Détection défaut ;
Mots-clés espagnols / Spanish Keywords
Circuito integrado ; Circuito lógico ; Herramienta software ; Factor mérito ; Circuito numérico ; Diseño circuito ; Reducción ruido ; Simulación lógica ; Modelo lógico ; Tecnología MOS complementario ; Transistor ; Lenguaje VHDL ; Circuito VLSI ; Detección imperfección ;
Mots-clés d'auteur / Author Keywords
Fault security ; Fault modeling ; VHDL ; CMOS defects ;
Localisation / Location
INIST-CNRS, Cote INIST : 20219, 35400011647485.0050

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