ASIC Verification Services:

Verification & Validation


eInfochips enables you to rapidly build verification environments for complex, multimillion gate SoC verification, thereby shortening the verification cycle and saving on development cost. Our verification methodology helps build highly layered, scalable, reusable & extensible verification environments for module and SoC level verification, providing maximum functional coverage.

ASIC Verification Services:

* Functional Verification
* Code Coverage Analysis
* Assertion based Verification
* Bus Functional Modeling
* Hardware–Software Co-Verification
* Synthesizable Test Benches
* Protocol Monitors & Checkers
* Formal Verification
* System Simulation
* Full Chip Verification

eInfochips provides end to end verification assurance so that the customers can focus on more critical issues like product conceptualization, architecture, features, performance etc. eInfochips also enables accelerated verification of DUT with independently developed verification IPs. The availability of comprehensive transactions while reducing the simulation runtime also reduces the possibility of a bug staying un-detected.

ASIC Verification Tools Expertise:

Functional
Verification


Hardware Software
Co-verification


Assertion based Verification


Formal
Verification

Platforms:
Specman, VERA, SystemVerilog,SystemC

Simulators: IUS,NC-Sim, NC-Verilog, Verilog-XL, Questasim, Modelsim, VCS, FinSim

Lint tools: exploreRTL, VeriLint, SureLint, Verix

Code coverage:
CoverMeter, SureCov, HDLScore


Axis
Palladium
EVE
Mentor Seamless


0-in
Inhouse Assertions


Verplex, 0-in
Averant
IFV
Conformal
LEDA

ASIC Verification Language Expertise:

Functional Verification


Hardware Software Co-verification


Assertion Based Verification


Formal Verification

HDL:
Verilog, VHDL

HVL:
e, VERA,SV, SC

Other:
C. C++

Script:
Perl, Shell script, Tcl/Tk


HDL:
Verilog, VHDL

Other:
C. C++

Script:
Perl, Shell script, Tcl/Tk


PSL
SVA
OVA


HDL:
Verilog, VHDL

Our capabilities in Verification include:

* Expertise in HDLs and HVLs
* Full chip verification including IP Cores, automated test benches & regression environment
* Development of regression suites in Specman Elite, C/C++, Vera, Perl and Shell scripts, PLI based verification
* Bus functional models, Protocol monitors and checkers
* Developing automated test benches to create logic and timing verification environment
* Functional and Code coverage analysis
* Experience of working on multi-million gate ASIC / SoC design verification projects
* Extensive portfolio of Verification Components
* Experience in design and verification, and domain knowledge of various technologies like PCI, Ethernet, Fiber Channel, SAS, UWB, USB, I2C, PCI Express, SATA, SPI, HDMI etc.
* Complete verification solutions right from test plan documentation to seeing the silicon tape-out