ASIC Design
We offer multi million gate high frequency SoC design services at latest process nodes for some of the most demanding applications in wireless, networking, computer and consumer electronics. We accelerate product development using proven methodologies, ready to use building block IPs, and a team with over 10 years experience in taking designs to Silicon and state-of-the-art EDA tools. We can deliver a finished ASIC with the help of our foundry partners and can help in testing, assembly and packaging as well.
Technologies
0.13,0.18, 0.25 & 0.35 ยต logic/Mixed Signal CMOS
Offerings
* Specification to ASIC/GDS-II
o RTL to GDSII
o Netlist to GDSII
* Verification Solutions – Test Environment build up, Test Bench, VIPs, BFMs
* DFT – Full Scan and Embedded
* FPGA/ASIC Re-targeting
* Prototyping Services(Xilinx, Altera,)
* Technology migration
* SOC – IP integration, Verification, tapeout
* Analog and Mixed Signal (AMS) design
o PLLs,
o Data Converters,
o Interfaces such as LVDS IO’s
o VCOs,
o Amplifiers, Comparators etc..
Design tools
* Front end: Mentor, Cadence & Synopsys Simulators, Verilint, Surecov for code coverage
* Back end: Synopsys, Cadence, Mentor and Proprietary tools
* FPGA: Synplify-Pro, Leonardo Spectrum & FPGA Express synthesis. Xilinx, Altera tools
Analog Environment - Cadence Analog Artist
* Cadence Composer
* Avant! HSPICE
* Mentor Graphics Eldo
* Cadence Spectre
* Cadence Virtuoso
* Cadence Dracula
* Cadence Diva
* Cadence Assura
Deliverables
* ASIC, Board, Drivers
* GDS-II, Source Code for Digital part
* Mixed Signal ASIC GDS-II Database
* Composer Schematics Database for Analog part
* SPICE Netlist for Analog part
* Maintenance support
* Test Bench with BFMs and VIPs
* FPGA Prototypes
* Synthesis and Test Scripts
* Assistance in Certification –WHQL, Standard bodies
Success Stories
* Gigabit/10 GB Ethernet
* IEEE 1394 a
* WLAN 802.11
* PCI/PCIX
* USB
* Network Security
* 400MHz/800MHz PLL
* 1.25GHz VCO
* LVDS IO
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Tuesday, October 7, 2008
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