Intellectual Property

Intellectual Property (IP)



eInfochips’ Intellectual Property covers a wide spectrum of semiconductor design and verification solutions. Our IPs play an instrumental role in reducing the design and verification time for complex SoCs (System-on-Chip) and help you reach your market faster.
eInfochips is now offering ASIC Design IPs and Verification IPs for evaluation.

Design IPs
(Verilog)


Bus


AHB to APB Bridge
APB to slave interface
AXI Slave
DDR
NAND Flash Controller (FPGA tested)
PCI master & target (FPGA tested)

Video Processor Core


CSC
GCR
AES
IMR
IDCT
DCT
LUT FIR
DPRAM FIR

Serial Protocol


SPI 3
SPI 5.0
UART

* The design entry of these IP cores is done in Verilog HDL.
* These are fully synthesized IP cores and are tested on Xilinx FPGAs.
* The cores are designed to be optimal in terms of power, speed and area. Detailed documentation on design, functional verification and configuration is available.
* The IP cores can be modified to suit specific design requirements and can also be integrated with customer IP easily.

Verification IP



Verification IPs


Bus & Protocols


PCI/PCI-x (eVC)
SPI (eVC, Alpha)
AMBA AHB (SV)
SPI 4 P2 (UVC, Beta)

Serial Protocol


XAUI (UVC)
I2C (SV & UVC, Alpha)
SAS (System C)
PS2 (eVC, Alpha)
SONET (eVC, Beta)
UWB (System C)
Serial ATA (System C)
Gigabit Ethernet (eVC)
PCI express (eVC)

* All verification components are configurable, reusable plug-and-play verification solutions
* The verification components are developed at eInfochips by leveraging our rich experience in ASIC/SoC design verification and expertise in HVLs SystemVerilog, Vera, SystemC and e.





Project Examples:

The DDR IO Cell is a high-performance & low latency controller interface to DRAM memory system. The general-purpose cell is independent of logical memory controller design thus enabling support for a wide variety of memory applications more...

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