VHDL for FPGAImpulse - Design Acceleratio

Impulse CoDeveloper C to VHDL for FPGAImpulse - Design Acceleratio

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Accelerate your embedded software applications!
The key to success when implementing software algorithms in hardware is to find and exploit parallelism in your applications. The more parallelism you can achieve, the higher the performance will be. When it comes to exploiting parallelism, there are two fundamental areas where CoDeveloper can help.

1. Automated C to hardware compilation

CoDeveloper's advanced hardware compilation technology is capable of extracting parallelism from standard C statements, including blocks of statements that span multiple C source file lines or entire loop bodies. There is no need to insert explicit statements or keywords (such as "par" statements) in order to exploit parallelism within your C applications. Instead, the CoDeveloper compiler analyzes the statements in your C language description, optimizes those statements and, when possible, combines multiple statements into a single instruction stage representing one clock cycle. You can express control over this process (for example by specifying blocks of statements that are to be pipelined, or loops that are to be unrolled) but in general it is not necessary to understand or describe statement-by-statement parallelism in your Impulse C applications in order to generate parallel hardware.

The hardware compilation features of CoDeveloper include:

* Common compiler optimizations such as common sub-expression elimination, constant folding and dead code elimination
* Automatic parallelizing of multiple, sequential C statements into equivalent instruction stages
* User-controllable instruction stage pipelining (a pipeline pragma)
* User-controllable instruction stage delays (a stagedelay pragma)
* User-controllable loop unrolling (the unroll pragma)
* Automatic generation of synthesizable RTL from C processes
* Automatic generation of hardware-to-hardware and hardware-to-software interfaces, including dual-clock interfaces

2. Support for a multi-process programming model

While compiler optimizations and automated parallelism extraction are important, equally important is giving the programmer control over coarse-grained, system-level parallelism. This is provided in Impulse C through the following library features:

* Processes, allowing multiple, parallel units of computation to be described and interconnected
* Streams, which provide an efficient, self-synchronizing method of data movement between parallel processes
* Shared memories (and associated block read and block write functions), which provide an alternate method of data communication useful for static or randomly accessed data
* Signals, which provide a means of synchronizing processes to specific events or conditions
* Registers, which provide a direct, unbuffered means of passing data into and out of hardware processes.
* A configuration function that allows a complete Impulse C application consisting of multiple parallel processes to be created, and allows the necessary inter-process communication channels (typically streams, signals and/or shared memories) to be described.

These parallel programming features of Impulse C provide a programming model and a desktop verification methodology allowing system-level parallelism to be explicitly defined by the programmer, while lower level parallelism (the inner code loops and compute-intensive operations that represent actual algorithms) are automatically exploited by the Impulse CoDeveloper compiler.

Get started fast

CoDeveloper includes extensive documentation and sample projects that help you get started fast. Platform-specific, step-by-step tutorials show you how to create multi-process, highly parallel applications entirely in C language and compile them to mixed hardware/software platforms such as the FPGA development board shown below.