Floorplanning Methods

7.2. Floorplanning Methods
Floorplanning is chip-level layout design. When designing a leaf cell, we used transistors and vias as our basic components; floorplanning uses the adders, registers, and FSMs as the building blocks. The fundamental difference between floorplanning and leaf-cell design is that floorplanning works with components that are much larger than the wires connecting them. This great size mismatch forces us to analyze the layout differently and to make different trade-offs during design.

Many chips are composed from cells of a variety of shapes and sizes, as shown in Figure 7-1. We call the layout cells blocks during floorplanning because we use them like building blocks to construct the floorplan. In bricks-and-mortar style layout, the cells may have radically different sizes and shapes. The layout program must place the components on the chip by position and orientation, leaving sufficient space between the components for the necessary wires. Blocks may be redesigned to change their aspect ratio in order to improve the floorplan. As we will see, the more complex traffic pattern of wiring areas makes routing wires in a bricks-and-mortar layout much harder than in a standard cell layout. (Some people use the term standard cell for any layout, including brick-and-mortar, which is built from pre-designed components. Since standard cell is a much abused term, be sure you understand its meaning in the context in which it is used.)


Figure 7-1. A typical layout, built from a variety of styles.





The next example shows the floorplan for a large chip.

Example 7-1. Floorplan of the IBM Power 2 Super Chip
The Power 2 Super Chip (P2SC) is a large microprocessor. It has over 15 million transistors (5.7 million logic, 9.3 million cache) on an 18.2x18.4mm2 die. The chip is fabricated in a 0.27μm, 5-level-metal process. The chip comes in 120 and 135 MHz versions.

The chip photomicrograph has been overlaid below with the floorplan showing the major functional units:

Photo courtesy of IBM.
Tom Way, IBM Microelectronics, Essex Junction, VT


This chip is large enough that each of the units in the chip-level floorplan has its own internal floorplan. The DCU units contain memory arrays as well as driver and control logic. The ICU unit contains several data paths along with the necessary control logic.