asic design: October 2008

Wednesday, October 29, 2008

VHDL reference material Contents

VHDL reference material
Contents
# Using Cadence VHDL on GL machine
# Compact Summary of VHDL
# Printable Compact Summary of VHDL
# Sample VHDL code
# VHDL-handbook.pdf
# VHDL designers guide
# VHDL Cookbook in PostScript
# GHDL Download free VHDL compiler and simulator
# Download free VHDL compiler and simulator
# VHDL intro by Francis Bruno in PostScript
# VHDL project by Francis Bruno in PostScript
# VCOMP/VSIM from University of Pittsburgh
# Using FTL Systems Exploration VHDL
# VHDL standard packages and types
# FPGA and other CAD information
# Draft of IEEE Standard VHDL Language
# Other Links
Using Cadence VHDL on GL machine

First: You must have an account on a GL machine. Every student
and faculty should have this.
Either log in directly to cadence.gl.umbc.edu or
Use ssh cadence.gl.umbc.edu

Be in your login directory, else some files need changing.
You can copy many sample files to your working directory using:
cp /afs/umbc.edu/users/s/q/squire/pub/download/cs411.tar .
There are many files available.

Next: Follow instructions exactly or you figure out a variation.
1) Get this tar file into your home directory (on /afs i.e.
available on all GL machines.)
cs411.tar and then type commands:
cp /afs/umbc.edu/users/s/q/squire/pub/download/cs411.tar .
tar -xvf cs411.tar
cd vhdl
mv Makefile.cadence Makefile
tcsh
source vhdl_cshrc
make
more add32_test.out
make clean # saves a lot of disk quota

Then do your own thing with Makefile for other VHDL files

2) The manual, step by step method (same results as above)
Be in your home directory.
mkdir vhdl # for your source code .vhdl .vhd
cd vhdl
mkdir vhdl_lib # your WORK library, keep hands off

You now need to get the following 6 files into you vhdl directory:
vhdl_cshrc
cds.lib change $HOME to your path if needed
hdl.var
Makefile.cadence for first test
add32_test.vhdl for first test
add32_test.run for first test

Make the following modification to cds.lib :
Edit and replace $HOME with the specific path to your home if needed
directory. e.g. /home/grad4/auser12

mv Makefile.cadence Makefile
# Run the test run:
source vhdl_cshrc
make # should be no error messages
more add32_test.out # it should have VHDL simulation output
make clean

You are on your own to write VHDL and modify the Makefile.
Remember each time you log on:
cd vhdl
tcsh
source vhdl_cshrc
make # or do your own thing.

The above is the latest generation Cadence "IUS" "ncvhdl, nceval, ncsim"

GHDL

You can download a free VHDL system form ghdl.free.fr
Follow the instructions for Windows, Linux or MAC OSX

We have tried to get the Linux version onto linux.gl.umbc but
have been unsucessful, it has been installed on personal Linux
machines using root password and installing into /usr/local tree.

The Windows version is a little different, yet it works.

For CMSC 411, you need to do a little extra because GHDL does
not default with some IEEE packages we use.

Using GHDL on your home PC in windows:

Download GHDL from ghdl.free.fr/download.html
click on "installer"
After installing, control panel -> system -> advanced ->
environment variables -> user variables, path, edit
Add to your user path ;C:\"program files"\Ghdl\bin

From a Command prompt window type or use add32_test.bat

rem use GHDL to analyze, elaborate and run add32_test.vhdl
ghdl -a --ieee=synopsys add32.vhdl
ghdl -a --ieee=synopsys add32_test.vhdl
ghdl -e --ieee=synopsys add32_test
ghdl -r --ieee=synopsys add32_test --stop-time=160ns > add32_test.out

Look at file add32_test.out with your favorite editor.

The 160ns is found in the file add32_test.run

The "diff" command on Windows is "fc", ignore the few lines at
beginning and end of comparison of .chk files.

Using FTL Systems Exploration VHDL

First: Read Appendix H of Ashenden's book, p723
The steps are: load the CD, make a registration file,
EMail the file, get back a license file, download the
VHDL analyzer/compiler and simulator.

Then: Follow the Quick Start Guide on page 728.

VHDL Cookbook (PostScript files)

The following eight PostScript files provide an introduction to VHDL

* Contents
* Chapter 1
* Chapter 2
* Chapter 3
* Chapter 4
* Chapter 5
* Chapter 6
* Chapter 7
* BNF for VHDL 93, plain text

The above is by Peter Ashenden who now has an updated version out
as books: "The Student's Guide to VHDL" ISBN 1-55860-520-7 and
"The Designer's Guide to VHDL" second edition ISBN 1-55860-674-2

Examples of VHDL from Ashenden's Designer's Guide are here

Download free VHDL compiler and simulator

This is how I downloaded and installed a free VHDL compiler
and simulator on Windows and Linux systems. It is not 100%
compatible with Cadence, Cadence allows a few non standard constructs,
but it works on many circuits and features.

The Cadence version on cadence.gl.umbc.edu has many bugs not
on cadence1.cs.umbc.edu. For example: alias swrite ... does not work.
A syntax error hangs with a phoney "lock" message.

Using browser: www.symphonyeda.com/proddownloads.htm

Choose Windows ~9.3MB or
Linux ~9.3MB

Execute the Windows file, choose 'setup' and follow instructions

untar the Linux version and follow instructions

For CMSC 411 the project check files are .chks for this VHDL.

VHDL intro by Francis Bruno (PostScript files)

The following four PostScript files provide
Francis Bruno's introduction to VHDL

* Title Page
* Table of Contents
* Body
* Appendix

VHDL project by Francis Bruno (PostScript files)

The following four PostScript files plus index and .tar.gz
files provide Francis Bruno's VHDL project.

* Title Page
* Table of contents
* Body
* Appendix
* Bruno index to models
* VHDL source code as .tar.gz

VCOMP/VSIM from PITT (PostScript file)

The following PostScript file provides an introduction to VHDL
and instructions for compiling and simulating using vcomp/vsim.

* VSIM manual

FPGA and other CAD information

You can get working chips from VHDL using synthesis tools.

One of the quickest ways to get chips is to use FPGA's,
Field Programmable Gate Arrays.
The two companies listed below provide the software and the
foundry for you to design your own integrated circuit chips:

www.altera.com

www.xilinx.com

Complete Computer Aided Design, CAD, packages are available from
companies such as Cadence, Mentor Graphics and Synopsis.

Draft of IEEE Standard VHDL Language

Draft 2000/D3 HERE

Other Links

* Hamburg VHDL Archive (the best set of links I have seen!)
* RASSP Project VHDL Tools
* VHDL Organization Home Page
* A slightly restrictive free version of a commercial VHDL compiler and simulator. Windows and Linux versions.
* gnu GPL VHDL for Linux, under development (no progress since Jan 29, 2002)
* More information on Exploration/VHDL from FTL Systems (seems dead in mid 2003)

Go to top

Last updated 10/3/08

VHDL reference material

Table of Contents

Basic Stimulus Generation
Testbench Structure
Definition of Terms
Writing to Files
Reading from Files
More Reading from Files
The World of Perl
SRAM modeling
Passive SRAM Model
Signal Monitors
Generating Clock and Reset Stimulus
Approaches to Test Generation
File Read Method
VHDL pre-processing Method
Test-specific Entities
Configuration controlled Test Selection
Using Transaction Logs
Using Transaction Logs II
Using Behavioural Models
Recommended Directory Structure
Test Strategy
The End

We start with VHDL

We start with VHDL
If You have a question regarding VHDL then its quite possible that some one else has asked it before. So the very first thing to do is hop over to the VHDL FAQ and check it out...
The VHDL FAQ - This FAQ is divided into 4 sections and is posted monthly to the VHDL Newsgroup
Part 1: FAQ General (contacts, etc.)
Part 2: Lists of Books on VHDL
Part 3: Lists of Products & Services (Freewares and Commercial stuff)
Part 4: Glossary
If the FAQ proves to be inadequete you can go ask the newsgroup
comp.lang.vhdl This is the VHDL News group and this is what the FAQ for this newsgroup says
"The newsgroup comp.lang.vhdl was created in January 1991. It's an international forum to discuss ALL topics related to the language VHDL which is currently defined by the IEEE Standard 1076/93. Included are language problems, tools that only support subsets etc. but NOT other languages such as Verilog HDL. This is not strict - if there is the need to discuss information exchange from EDIF to VHDL for example, this is a topic of the group. The group is unmoderated. Please think carefully before posting - it costs a lot of money! (Take a look into your LRM for example or try to search http://www.Deja.com/usenet - if you still cannot find the answer, post your question, but make sure, that other readers will get the point). "
Who wouldnt want a good low cost setup for dirtying their hands in HDL Design? Here is a starter kit.
Editor: The choice of editors is a very controversial subject, you may want to check out what others have to say about this by searching google groups for "VHDL editor" and also the stuff listed in the FAQ( part 3 ). For unix buff you can always go in for emacs/Xemacs and download the VHDL mode. Or else stick to good old vim and use the necessary stuff for syntax highlighting.
For windows users I have not tested any of the freely available editors.. but a port of emacs for windows is available.
Simulators: When It comes to simulators The preferred choice when the budget is good is the Industry Standard Modelsim. For those with limited budgets You can try Activevhdl.For those who believe that the good things in life come free... there is always the VHDL compiler from vanilla cad tools for linux and VHDL Simili from symphonyEDA for windows Until we see the guys at freehdl and gnu eda make any progress that is.
Synthesis: Unfortunately I cant think of any cheap/free good synthesis tools which can be used... the snapshots at mycad look good, but I have yet to try some thing other than synopsys until I find some really good free stuff you can use the stuff listed in the newsgroup FAQ and if you find anything worthy send me a mail...
Learning VHDL
There are quite a few good VHDL Tutorials and books available on the web
This list is but a drop in the ocean
VHDL Tutorial A javascript based tutorial which uses javascript to open new windows by Prof. Dr.-Ing. Wolfram H. Glauert of "Universität Erlangen-Nürnberg Lehrstuhl für Rechnergestützten Schaltungsentwurf"
VHDL Verification Course Suitable for those who already know the syntax and want to use the language for verification purpose
A Hardware Engineer's Guide to VHDL This VHDL tutorial assumes no prior knowledge of HDLs.
VHDL Language Guide Covers Language Overview, A First Look at VHDL, Objects, Data Types and Operators, Using Standard Logic, Concurrent Statements, Sequential Statements, Modularity Features, Partitioning Features, Test Benches, Keyword Reference, Examples Gallery
VHDL Tools
Code Generators
Statecad FSM to VHDL/Verilog generator (30days eval available)
CRC Tool Generates synthesizable CRC code in VHDL and Verilog
Models
LEON-1 VHDL model The LEON core is a SPARC* compatible integer unit developed for future space missions. It has been implemented as a highly configurable, synthesisable VHDL model. To promote the SPARC standard and enable development of system-on-a-chip (SOC) devices using SPARC cores, the European Space Agency is making the full source code freely available under the GNU LGPL license. Strasbourg UniversityAn ftp site containing VHDL utilities, papers, and VHDL code.
Other resources
hamburg VHDL Archive VHDL documents (FAQ, introductions to VHDL, etc.), VHDL-related papers, and public domain utilities.

One of the best places to look for HDL related information is the various online Directories

Google Web Directory - Science > Technology > Electronics > Design > Verilog_and_VHDL_Tools
Google Web Directory - Computers > Programming > Languages > VHDL
Programming > Languages > VHDL
Technology > Electronics > Design > Verilog and VHDL Tools

Discuss This section and any questions on the VHDL Language at the VHDL discussion board
Synthesis
VHDL SYNTHESIS TUTORIAL A tutorial on synthesis By Bob Reese of Electrical Engineering Department Mississippi State University.

Discuss synthesis tools and synthesis related issues at the synthesis page
VERILOG
Before going to the newsgroup at comp.lang.verilog it would be advisabe to check the FAQ while teh original FAQ is at http://www.landfield.com/faqs/verilog-faq/ It has been many moons since it has been updated :-( so many now make way to http://www.angelfire.com/in/verilogfaq/ which is the updated version of the previous
Resources and References
Chris Spear's Hot PLI Stuff
Project VeriPageVerilog Programming Language Interface(PLI) resources.
Google Web Directory - Computers > Programming > Languages > Verilog
TechOnLine: Courses
Doulos VHDL Training Verilog Training : A Hardware Designer?s Guide to Verilog
Coding Style Guide
Tekmos Verilog Style Manual Verilog coding syle manual used at Tekmos

Discuss Verilog and verilog coding related issues at the verilog discussion board
Misc Related sites
comp.arch.fpga This is for fpga related issues
Sites with list of downloadables
DACafe EDA DownloadsLinuxApps - If you can't find it here, you won't find it anywhere !!
Links to other free EDA software LinuxApps - If you can't find it here, you won't find it anywhere !! Electronics specific sublink
Scientific Applications on Linux (SAL)
MISC
answer to the usual question of wether to use vhdl or verilog.
Verilog HDL vs. VHDL For the First Time User
Other HDL stuff
VHDL-Online

Gerard's Personal Play Area Page
HDL's
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VHDL Arithmetic Functions

VHDL

The following examples provide instructions for implementing functions using VHDL. For more information on VHDL, refer to Quartus® II or MAX+PLUS® II software Help.
VHDL Embedded Processor Functions

* Standard Nios® II Hardware Design Example
* Full-Featured Nios II Hardware Design Example
* Small Nios II Hardware Design Example
* Fast Nios II Hardware Design Example
* Low-Cost Nios II Hardware Design Example

VHDL Arithmetic Functions

* Adder/Subtractor
* Carry Look-Ahead Adder
* Down Counter (lpm_counter)
* Behavioral Counter
* Ripple-Carry Adder

VHDL Memory Functions

* Dual Clock Synchronous RAM
* Single Clock Synchronous RAM
* Single Clock Synchronous RAM With Asynhcronous Read Address
* Cycle-Shared Dual-Port RAM (csdpram)
* Zero-Bus Turnaround (ZBT) Controller
* Quad Data Rate (QDR) SRAM Controller

VHDL Bus and I/O Functions

* Bidirectional Bus
* Tri-State Buses

VHDL Logic Functions

* 8x64 Shift Register With Taps
* Counter With Synchronous Load
* Preventing Unintentional Latch Creation
* Instantiating a DFFE
* Instantiating a DFF Using lpm_dff

VHDL Digital Signal Processing (DSP) Functions

* Cyclic Prefix Insertion for OFDM Systems
* Viterbi Decoder With Node Synchronization
* Signed Multiplier
* Signed Multiply-Accumulator
* Unsigned Multiplier With Registered I/O
* Unsigned Multiply-Adder

Other VHDL Functions

* Creating a Hierachical Design
* Converting a Hexadecimal Value to a Standard Logic Vector

How to Use VHDL Examples

Altera provides VHDL design examples as downloadable executable files or as text in your web browser. Click the executable file link to download the file to your hard disk. To use VHDL examples displayed as text in your Quartus II or MAX+PLUS II software, copy and paste the text from your web browser into the Quartus II or MAX+PLUS II software Text Editor. Make sure that the file name of the VHDL design file (.vhd) corresponds to the entity name in the example. For instance, if the entity name is myram, you should save the file as myram.vhd.
Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

VHDL & Verilog Compared & Contrasted

VHDL & Verilog Compared & Contrasted
Plus Modeled Example Written in
VHDL, Verilog and C
Douglas J. Smith
VeriBest Incorporated
e-mail: djsmith@veribest.com
Abstract
This tutorial is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their differences. The second part contains a worked example of a model that computes the Greatest Common Divisor (GCD) of two numbers. The GCD is modeled at the algorithmic level in VHDL, Verilog and for comparison purposes, C. It is then shown modeled at the RTL in VHDL and Verilog.
1. Introduction
There are now two industry standard hardware description languages, VHDL and Verilog. The complexity of ASIC and FPGA designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and mega cells written in either VHDL or Verilog. As a result, it is important that designers know both VHDL and Verilog and that EDA tools vendors provide tools that provide an environment allowing both languages to be used in unison. For example, a designer might have a model of a PCI bus interface written in VHDL, but wants to use it in a design with macros written in Verilog.
2. Background
VHDL (Very high speed integrated circuit Hardware Description Language) became IEEE standard 1076 in 1987. It was updated in 1993 and is known today as "IEEE standard 1076 1993". The Verilog hardware description language has been used far longer than VHDL and has been used extensively since it was launched by Gateway in 1983. Cadence bought Gateway in 1989 and opened Verilog to the public domain in 1990. It became IEEE standard 1364 in December 1995.

There are two aspects to modeling hardware that any hardware description language facilitates; true abstract behavior and hardware structure. This means modeled hardware behavior is not prejudiced by structural or design aspects of hardware intent and that hardware structure is capable of being modeled irrespective of the design's behavior.
3. VHDL/Verilog compared & contrasted
This section compares and contrasts individual aspects of the two languages; they are listed in alphabetical order.
Capability
Hardware structure can be modeled equally effectively in both VHDL and Verilog. When modeling abstract hardware, the capability of VHDL can sometimes only be achieved in Verilog when using the PLI. The choice of which to use is not therefore based solely on technical capability but on:

* personal preferences
* EDA tool availability
* commercial, business and marketing issues

The modeling constructs of VHDL and Verilog cover a slightly different spectrum across the levels of behavioral abstraction; see Figure 1.

HDL modeling capability

Figure 1. HDL modeling capability
Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it's own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.
Data types
VHDL. A multitude of language or user defined data types can be used. This may m ean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it's simplicity.
Design reusability
VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.
Easiest to Learn
Starting with zero knowledge of either language, Verilog is probably the easiest to grasp and understand. This assumes the Verilog compiler directive language for simulation and the PLI language is not included. If these languages are included they can be looked upon as two additional languages that need to be learned. VHDL may seem less intuitive at first for two primary reasons. First, it is very strongly typed; a feature that makes it robust and powerful for the advanced user after a longer learning phase. Second, there are many ways to model the same circuit, specially those with large hierarchical structures.
Forward and back annotation
A spin-off from Verilog is the Standard Delay Format (SDF). This is a general purpose format used to define the timing delays in a circuit. The format provides a bidirectional link between, chip layout tools, and either synthesis or simulation tools, in order to provide more accurate timing representations. The SDF format is now an industry standard in it's own right.
High level constructs
VHDL. There are more constructs and features for high-level modeling in VHDL than there are in Verilog. Abstract data types can be used along with the following statements:

* package statements for model reuse,

* configuration statements for configuring design structure,

* generate statements for replicating structure,

* generic statements for generic models that can be individually characterized, for example, bit width.

All these language statements are useful in synthesizable models.

Verilog. Except for being able to parameterize models by overloading parameter constants, there is no equivalent to the high-level VHDL modeling statements in Verilog.
Language Extensions
The use of language extensions will make a model non standard and most likely not portable across other design tools. However, sometimes they are necessary in order to achieve the desired results.

VHDL. Has an attribute called 'foreign that allows architectures and subprograms to be modeled in another language.

Verilog. The Programming Language Interface (PLI) is an interface mechanism between Verilog models and Verilog software tools. For example, a designer, or more likely, a Verilog tool vendor, can specify user defined tasks or functions in the C programming language, and then call them from the Verilog source description. Use of such tasks or functions make a Verilog model nonstandard and so may not be usable by other Verilog tools. Their use is not recommended.
Libraries
VHDL. A library is a store for compiled entities, architectures, packages and configurations. Useful for managing multiple design projects.

Verilog. There is no concept of a library in Verilog. This is due to it's origins as an interpretive language.
Low Level Constructs
VHDL. Simple two input logical operators are built into the language, they are: NOT, AND, OR, NAND, NOR, XOR and XNOR. Any timing must be separately specified using the after clause. Separate constructs defined under the VITAL language must be used to define the cell primitives of ASIC and FPGA libraries.

Verilog. The Verilog language was originally developed with gate level modeling in mind, and so has very good constructs for modeling at this level and for modeling the cell primitives of ASIC and FPGA libraries. Examples include User Defined Primitive s (UDP), truth tables and the specify block for specifying timing delays across a module.
Managing large designs
VHDL. Configuration, generate, generic and package statements all help manage large design structures.

Verilog. There are no statements in Verilog that help manage large designs.
Operators
The majority of operators are the same between the two languages. Verilog does have very useful unary reduction operators that are not in VHDL. A loop statement can be used in VHDL to perform the same operation as a Verilog unary reduction operator. VHDL has the mod operator that is not found in Verilog.
Parameterizable models
VHDL. A specific bit width model can be instantiated from a generic n-bit model using the generic statement. The generic model will not synthesize until it is instantiated and the value of the generic given.

Verilog. A specific width model can be instantiated from a generic n-bit model using overloaded parameter values. The generic model must have a default parameter value defined. This means two things. In the absence of an overloaded value being specified, it will still synthesize, but will use the specified default parameter value. Also, it does not need to be instantiated with an overloaded parameter value specified, before it will synthesize.
Procedures and tasks
VHDL allows concurrent procedure calls; Verilog does not allow concurrent task calls.
Readability
This is more a matter of coding style and experience than language feature. VHDL is a concise and verbose language; its roots are based on Ada. Verilog is more like C because it's constructs are based approximately 50% on C and 50% on Ada. For this reason an existing C programmer may prefer Verilog over VHDL. Although an existing programmer of both C and Ada may find the mix of constructs somewhat confusing at first. Whatever HDL is used, when writing or reading an HDL model to be synthesized it is important to think about hardware intent.
Structural replication
VHDL. The generate statement replicates a number of instances of the same design-unit or some sub part of a design, and connects it appropriately.

Verilog. There is no equivalent to the generate statement in Verilog.
Test harnesses
Designers typically spend about 50% of their time writing synthesizable models and the other 50% writing a test harness to verify the synthesizable models. Test harnesses are not restricted to the synthesizable subset and so are free to use the full potential of the language. VHDL has generic and configuration statements that are useful in test harnesses, that are not found in Verilog.
Verboseness
VHDL. Because VHDL is a very strongly typed language models must be coded precisely with defined and matching data types. This may be considered an advantage or disadvantage. However, it does mean models are often more verbose, and the code often longer, than it's Verilog equivalent.

Verilog. Signals representing objects of different bits widths may be assigned to each other. The signal representing the smaller number of bits is automatically padded out to that of the larger number of bits, and is independent of whether it is the assigned signal or not. Unused bits will be automatically optimized away during the synthesis process. This has the advantage of not needing to model quite so explicitly as in VHDL, but does mean unintended modeling errors will not be identified by an analyzer.
4. Greatest Common Divisor
Models of a greatest common divisor circuit is posed as problem and solution exercise. A model written in C is included in addition to VHDL and Verilog for comparison purposes.
4.1 Problem
The problem consists of three parts:

a) Design three algorithmic level models of an algorithm that finds the Greatest Common Divisor (GCD) of two numbers in the software programming language, C, and the two hardware description languages, VHDL and Verilog. Use common test data files to test the algorithm where practically possible. Neither the VHDL nor Verilog models need contain timing. All three models should automatically indicate a pass or fail condition.

b) Model the GCD algorithm at the RTL level for synthesis in both VHDL and Verilog. The model must be generic so that it can be instantiated with different bit widths. A Load signal should indicate when input data is valid, and a signal cal led Done, should be provided to signify when valid output data is available. The generic model should be verified with 8-bit bus signals.

c) Write VHDL and Verilog test harnesses for the two models that: 1) use the same test data files used by the algorithmic level models, and 2), instantiates both the RTL and synthesized gate level models so that they are simulated and tested at the same time.
4.2 Solution
The solution is broken into three parts corresponding to those of the problem. The solution parts use the following combined test and reference data files.

file: gcd_test_data.txt file: gcd_test_data_hex.txt
21 49 7 15 31 7 // Decimal 21 49 7
25 30 5 19 1E 5 // Decimal 25 30 5
19 27 1 13 1B 1 // Decimal 19 27 1
40 40 40 28 28 28 // Decimal 40 40 40
250 190 10 FA 6E A // Decimal 250 190 10
5 250 5 5 FA 5 // Decimal 5 250 5
4.2.1 Designing algorithmic level models in C, VHDL and Verilog
The algorithm used to find the greatest common divisor between two numbers is shown in Figure 2.

GCD Algorithm

Figure 2. GCD Algorithm

It works by continually subtracting the smaller of the two numbers, A or B, from the largest until such point the smallest number becomes equal to zero. It does this by continually subtracting B from A while A is greater than B, and then s wapping A and B around when A becomes less than B so that the new value of B can once again be continually subtracted from A. This process continues until B becomes zero.
C algorithmic model
The C model first declares integer values for the two inputs A and B, the computed output of the algorithm Y, and the reference output Y_Ref. Integer Y_Ref is the expected GCD result and used to compare with the computed result from the algorithm. The integer Swap is also declared and used in the algorithm to swap the two inputs A and B. A final integer, Passed, is used to indicate a pass (1) or fail (0) condition.

A file pointer (file_pointer) is defined in order to access the test data file "gcd_test_data.txt". It is opened for read mode only. Integer Passed is initially set to 1 and only set to 0 if the algorithm fails.

Reading test data file. The test data file contains three numbers on each line corresponding to values of A, B and Y_Ref respectively. A while loop is used to: 1) read each line of the test data file, 2) assign the three values to A, B and Y_Ref respectively, 3) use A and B to compute the GCD output Y, and 4) compare Y with Y_Ref. This while loop continues while there is test data in the test data file.

Algorithm implementation. The initial if statement is an extra check that both A and B are not zero. The algorithm is then modeled using two while statements. The first, outer-most, while statement checks to see if B has reached zero; if it has the GCD has been found. The second, inner-most, while statement checks to see if A is greater than or equal to B; if it is, it continually subtracts A from B and puts the result back in A. When A becomes less than B the inner most while loop completes, A and B are swapped using Swap, and the outer most while statement rechecks B to see if it has reached zero.

Testing the result. The algorithm is tested using an if statement which tests to see if the computed result Y is the same as the expected result Y_Ref. If they are different an error message is printed to the screen and Passed assigned the value 0. Finally, when all tests have completed and Passed is still equal to 1 a passed message is printed to the screen.
C algorithmic level model
#include
main ()
{
int A_in, B_in, A, B, Swap, Y, Y_Ref, Passed;
FILE *file_pointer;
file_pointer = fopen("gcd_test_data.txt", "r");
Passed = 1;
while (!feof(file_pointer))
{
/*------------------------------------*/
/* Read test data from file */
/*------------------------------------*/
fscanf (file_pointer, "%d %d %d\n", &A_in, &B_in, &Y_Ref);
/*----------------------------------*/
/* Model GCD algorithm */
/*----------------------------------*/
A = A_in;
B = B_in;
if (A != 0 && B != 0)
{
while (B != 0)
{
while (A >= B)
{
A = A - B;
}
Swap = A;
A = B;
B = Swap;
}
}
else
{
A = 0;
}
Y = A;
/*------------------------------*/
/* Test GCD algorithm */
/*------------------------------*/
if (Y != Y_Ref)
{
printf ("Error. A=%d B=%d Y=%d Y_Ref= %d\n", A_in, B_in, Y, Y_Ref);
Passed = 0;
}
}
if (Passed = 1) printf ("GCD algorithm test passed ok\n");
}
VHDL algorithmic level model
The VHDL model follows exactly the same principle as defined for the C model. When reading the integer values from the test date file they must be read and assigned to a variable; they cannot be read and assigned to a signal. As this is an algorithmic level model defined in a single entity it contains no input or outputs, nor does it contain any internal signals or associated timing. All computations use variables; variables are read from the test data file, the algorithm computes the result and variables are written to a results file.
VHDL algorithmic level model
library STD;
use STD.TEXTIO.all;
entity GCD_ALG is
end entity GCD_ALG;
architecture ALGORITHM of GCD_ALG is
--------------------------------------------
-- Declare test data file and results file
--------------------------------------------
file TestDataFile: text open
read_mode is "gcd_ test_data.txt";
file ResultsFile: text open write_mode is
"gcd_alg _test_results.txt";
begin
GCD: process
variable A_in, B_in, A, B, Swap, Y, Y_Ref: integer range 0 to 65535;
variable TestData: line;
variable BufLine: line;
variable Passed: bit := '1';
begin
while not endfile(TestDataFile) loop
-------------------------------------
-- Read test data from file
-------------------------------------
readline(TestDataFile, TestData);
read(TestData, A_in);
read(TestData, B_in);
read(TestData, Y_Ref);
------------------------------------
-- Model GCD algorithm
------------------------------------
A := A_in;
B := B_in;
if (A /= 0 and B /= 0) then
while (B /= 0) loop
while (A >= B) loop
A := A - B;
end loop;
Swap:= A;
A := B;
B := Swap;
end loop;
else
A := 0;
end if;
Y := A;
---------------------------------
-- Test GCD algorithm
---------------------------------
if (Y /= Y_Ref) then -- has failed
Passed := '0';
write(Bufline, st ring'("GCD Error: A="));
write(Bufline, A_in);
write(Bufline, string'(" B="));
write(Bufline, B_in);
write(Bufline, string'(" Y="));
write(Bufline, Y);
write(Bufline, string'(" Y_Ref="));
write(Bufline, Y_Ref);
writeline(ResultsFile, Bufline);
end if;
end loop;
if (Passed = '1') then -- has passed
write(Bufline, string' ("GCD algorithm test has passed"));
writeline(ResultsFile, Bufline);
end if;
end process;
end architecture ALGORITHM;
Verilog algorithmic level model
The Verilog model also follows the same principle as defined above for the C model. A major difference in this model is that Verilog cannot read decimal integer values from a system file. Data read from a system file must be:

1) read using one of the two language define system tasks, $readmemh or $readmemb and

2) stored in a memory, which has specific width and depth. This limits any read data to being in either hexadecimal or binary format. In this case a separate test d ata file is used "gcd_test_data_hex.txt" which has the test data specified in hexadecimal format.
Verilog algorithmic level model
module GCD_ALG;
parameter Width = 8;
reg [Width-1:0] A_in, B_in, A, B, Y, Y_Ref;
reg [Width-1:0] A_reg,B_reg,Swap;
parameter GCD_tests = 6;
integer N, M;
reg Passed, FailTime;
integer SimResults;
// Declare memory array for test data
// ----------------------------------
reg [Width-1:1] AB_Y_Ref_Arr[1:GCD_tests*3];
//----------------------------------
// Model GCD algorithm
//----------------------------------
always @(A or B)
begin: GCD
A = A_in;
B = B_in;
if (A != 0 && B != 0)
while (B != 0)
while (A >= B) begin
A = A - B;
Swap = A;
A = B;
B = Swap;
end
else
A = 0;
Y = A;
end
//------------------------------
// Test GCD algorithm
//-----------------------------
initial begin
// Load contents of
// "gcd_test_data.txt" into array.
$readmemh("gcd_test_data_hex.txt", AB_Y_Ref_Arr);
// Open simulation results file
SimResults = $fopen("gcd.simres");
Passed = 1;
/ Set to 0 if fails
for (N=1; N<=GCD_tests; N=N+1) begin
A_in = AB_Y_Ref_Arr[(N*3)+1];
B_in = AB_Y_Ref_Arr[(N*3)+2];
Y_Ref=AB_Y_Ref_Arr[(N*3)+3];
#TestPeriod
if (Y != Y_Ref) begin // has failed
Passed = 0;
$fdisplay (SimResults, " GCD Error:
A=%d B=%d Y=%d. Y should be %d", A_in, B_in, Y, Y_Ref);
end
end
if (Passed == 1) // has passed
$fdisplay (SimResults, "GCD algorithm test ha s passed");
$fclose (SimResults);
$finish;
end
endmodule
4.2.2 Designing RTL hardware models in VHDL and Verilog
The models have additional inputs and outputs over and above that of the algorithmic models. They are inputs Clock, Reset_N and Load, and the output Done. When Load is at logic 1 it signifies input data is available on inputs A and B, and are loaded into separate registers whose output signals are called A_hold and B_ hold. The extra output signal, Done, switches to a logic 1 to signify the greate st common divisor has been computed. It takes a number of clock cycles to comput e the GCD and is dependent upon the values of A and B.

The models are broken down into three process (VHDL)/always (Verilog) statements.

First process/always statement LOAD_SWAP. Infers two registers which operate as follows:

1) When Reset_N is at a logic 0, A_hold and B_hold are set to zero.

2) When not 1) and Load is at logic 1, data on A and B is loaded into A_hold and B_hold.

3) When not 1) or 2) and A_hold is less than B_hold, values on A_hold and B_hold are swapped, that is, A_hold and B_hold are loaded into B_hold and A_hold respectively.

4) When not 1), 2) or 3), A_hold is reloaded, that is, it keeps the same value. The value of A_hold - B_hold, from the second process/always statement, is loaded into B_hold.

Second process/always statement SUBTRACT_TEST. The first if statement tests to see if A_hold is greater than or equal to B_hold. If it is, the subtraction, A_hold - B_hold, occurs and the result assigned to A_New ready to be loaded into B_hold on the next rising edge of the clock signal. If A_hold is less than B_hold, then subtraction cannot occur and A_New is assigned the value B_hold so that a swap occurs after the next rising edge of the clock signal. The second if statement checks to see if the value of B_hold has reached zero. If it has, signal Done is set to logic 1 and the value of A_ hold is passed to the output Y through an inferred multiplexer function.

It is a requirement of the problem to synthesize the generic model with 8-bit bus signals. This is easily achieved in Verilog model by setting the default parameter value Width to 8. This means it does not need to be separately instantiat ed before it can be synthesized and have the correct bit width. This is not the case in VHDL, which uses a generic. The value of the generic is only specified when the model is instantiated. Although the VHDL model will be instantiated in the test harness, the test harness is not synthesized. Therefore, in order to synthesize an 8-bit GCD circuit a separate synthesizable model must be used to instantiate the RTL level model which specifies the generic, Width, to be 8. The simulation test harness does not need to use this extra model as it too, will specify the generic, Width, to be 8.
VHDL RTL model
library IEEE;
use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;
entity GCD is
generic (Width: natural);
port (Clock,Reset,Load: in std_logic;
A,B: in unsigned(Width-1 downto 0);
Done: out std_logic;
Y: out unsigned(Width-1 downto 0));
end entity GCD;
architecture RTL of GCD is
signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0);
signal A_lessthan_B: std_logic;
begin
----------------------------------------------------
-- Load 2 input registers and ensure B_Hold < A_Hold
---------------------------------------------------
LOAD_SWAP: process (Clock)
begin
if rising_edge(Clock) then
if (Reset = '0') then
A_Hold <= (others => '0');
B_Hold <= (others => '0');
elsif (Load = '1') then
A_Hold <= A;
B_Hold <= B;
else if (A_lessthan_B = '1') then
A_Hold <= B_Hold;
B_Hold <= A_New;
else A_Hold <= A _New;
end if;
end if;
end process LOAD_SWAP;
SUBTRACT_TEST: process (A_Hold, B_Hold)
begin
-------------------------------------------------------
-- Subtract B_Hold from A_Hold if A_Hold >= B_Hold
------------------------------------------------------
if (A_Hold >= B_Hold) then
A_lessthan_B <= '0';
A_New <= A_Hold - B_Hold;
else
A_lessthan_B <= '1';
A_New <= A_Hold;
end if;
-------------------------------------------------
-- Greatest common divisor found if B_Hold = 0
-------------------------------------------------
if (B_Hold = (others => '0')) then
Done <= '1';
Y <= A_Hold;
else
Done <= '0';
Y <= (others => '0');
end if;
end process SUBTRACT_TEST;
end architecture RTL;
Verilog RTL model
module GCD (Clock, Reset, Load, A, B, Done, Y);
parameter Width = 8;
input Clock, Reset, Load;
input [Width-1:0] A, B;
output Done;
output [Width-1:0] Y;
reg A_lessthan_B, Done;
reg [Width-1:0] A_New, A_Hold, B_Hold, Y;
//-----------------------------------------------------
// Load 2 input registers and ensure B_Hold < A_Hold
//-----------------------------------------------------
always @(posedge Clock)
begin: LOAD_SWAP
if (Reset) begin
A_Hold = 0;
B_Hold = 0;
end
else if (Load) begin
A_Hold = A;
B_Hold = B;
end
else if (A_lessthan_B) begin
A_Hold = B_Hold;
B_Hold = A_New;
end
else
A_Hold = A_New;
end
always @(A_Hold or B_Hold)
begin: SUBTRACT_TEST
//--------------------------------------------------
// Subtract B_Hold from A_Hold if A_Hold >= B_Hold
//--------------------------------------------------
if (A_Hold >= B_Hold) begin
A_lessthan_ B = 0;
A_New = A_Hold - B_Hold;
end
else begin
A_lessthan_B = 1;
A_New = A_Hold;
end
//----------------------------------------------
// Greatest common divisor found if B_Hold = 0
//----------------------------------------------
if (B_Hold == 0) begin
Done = 1;
Y = A_Hold;
end
else begin
Done = 0;
Y = 0;
end
end
endmodule
5. Conclusions
The reasons for the importance of being able to model hardware in both VHDL and Verilog has been discussed. VHDL and Verilog has been extensively compared and contrasted in a neutral manner . A tutorial has been posed as a problem and solution to demonstrate some language differences and indicated that hardware modeled in one language can also be modeled in the other. Room did not allow test harness models to be included in this tutorial paper, but is shown in the book "HDL Chip Design" [1]. The choice of HDL is shown not to be based on technical capability, but on: personal preferences, EDA tool availability and commercial, business and marketing issues.

REFERENCES: [1] HDL Chip Design, A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog by Douglas J Smith, published by Doone Publications.

[ Verilog FAQ | Tips | Online Books | Papers | Free Stuff | Tools | Jobs | What's New ] Copyright Rajesh Bawankule 1997-2003

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HDL Open Source Models, etc.

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GPL / Open Source EDA / HDL Tools

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Other EDA / CAD Groups

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* P1076 Standard VHDL Language Reference Manual (VASG)
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Government Electronics and Information Technology Association (GEIA)

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(see also IBIS)
* Rule Augmented Interconnect Layout (RAIL)
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* Electronic Data Interchange Format (EDIF) (The www.edif.org link is no longer valid.)

The Virtual Library EE page is a good source of links to other electrical engineering design resources.
EDA Industry Standing Conferences

* HDL Conference (HDLCON)
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* IC CAD (ICCAD)
* International Symposium on Physical Design (ISPD)
* DesignCON (DesignCON)

Books

* Books listed in the FAQ for the newsgroup comp.lang.vhdl
* Amazon.com listings for VHDL, Verilog, and EDA

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Thursday, October 23, 2008

IMAGES OF VLSI 3

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VLSI APPLICATIONS

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A CMOS digitally programmable filter technique for VLSI applications

Abstract

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 mu m standard CMOS chips are provided.

Item Type: Article
Date: May 2008
Date Type: Publication
Subjects: General
Department: General
Authors: Alzaher, HA
Authors Email: alzaherh@kfupm.edu.sa
ID Code: 16016
Deposited By: Mr. admin admin
Deposited On: 09 Aug 2008 11:46
Last Modified: 09 Aug 2008 11:50

THE L∞ VORONOI DIAGRAM OF SEGMENTS AND VLSI APPLICATIONS

THE L∞ VORONOI DIAGRAM OF SEGMENTS AND VLSI APPLICATIONS
Extended Abstract appeared in Proc. 9th International Symposium on Algorithms and Computation, December 1998, Taejon, Korea, LNCS 1533, 9–18.

Author(s):
EVANTHA PAPADOPOULOU
IBM TJ Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA
evanthia@watson.ibm.com
D. T. LEE
Supported in part by the National Science Foundation under the Grant CCR-9731638, and by the National Science Council under the grants NSC89-2213-E-001-012, NSC89-2219-E-001-002, and NSC89-2219-E-001-003. Also with the Department of Electrical Engineering and Computer Science, University of Illinois at Chicago, Chicago, IL 60607-7053.
Institute of Information Science, Academias Sinica, Nankang, Taipei, Taiwan, ROC
dtlee@iis.sinica.edu.tw

Keyword(s): Voronoi diagram
L ∞ metric
algorithmic degrees
critical areas
VLSI layout

Subject: Computer Science
Mathematics

Source:
International Journal of Computational Geometry & Applications (IJCGA)
Year: 2001 Vol: 11 Issue: 5 (October 2001) Page: 503 - 528

History: Received: 16 May 1999
Revised: 27 December 2000

DOI: 10.1142/S0218195901000626

Full Text: S0218195901000626.pdf
Abstract: In this paper we address the L∞ Voronoi diagram of polygonal objects and present application in VLSI layout and manufacturing. We show that L∞ Voronoi diagram of polygonal objects consists of straight line segments and thus it is much simpler to compute than its Euclidean counterpart; the degree of the computation is significantly lower. Moreover, it has a natural interpretation. In applications where Euclidean precision is not essential the L∞ Voronoi diagram can provide a better alternative. Using the L∞ Voronoi diagram of polygons we address the problem of calculating the critical area for shorts in a VLSI layout. The critical area computation is the main computational bottleneck in VLSI yield prediction.

Function Smoothing with Applications to VLSI Layout

Function Smoothing with Applications to VLSI Layout
Ross Baldick1, Andrew B. Kahng2, Andrew Kennings3 and Igor L. Markov4
1Dept. ECE, University of Texas, Austin, TX 78712-1084
2UCLA CS Dept., Los Angeles, CA 90095-1596
3Dept. ECE, Ryerson Polytechnic Univ., Toronto, ON, M5B 2K3
4UCLA Mathematics Dept., Los Angeles, CA 90095-1555
baldick@ece.utexas.edu, abk@cs.ucla.edu, akenning@ee.ryerson.ca, imarkov@math.ucla.edu

Multidimensional binary search trees

A deterministic algorithm for VLSI block placement was developed in this paper through human's accumulated experience in solving "packing" problem. Rectangle packing problem is just a simplified case of the polygon-shape stone plate packing problem that the ancient masons needed to face. Several "packing" principles derived from the so-called "less flexibility first" experience of the masons. A k-d tree data structure is used for manipulating the packed rectangles under the derived packing principles. Experiment results demonstrate that the algorithm is effective and promising in building block layout application.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1

D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States

2

Hidetoshi Onodera , Yo Taniguchi , Keikichi Tamaru, Branch-and-bound placement for building block layout, Proceedings of the 28th conference on ACM/IEEE design automation, p.433-439, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127708]

3

Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States

4

Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States

5

Jin Xu , Pei-Ning Guo , Chung-Kuan Cheng, Cluster refinement for block placement, Proceedings of the 34th annual conference on Design automation, p.762-765, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266366]

6

Pei-Ning Guo , Chung-Kuan Cheng , Takeshi Yoshimura, An O-tree representation of non-slicing floorplan and its applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.268-273, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309928]

7

Xianlong Hong , Gang Huang , Yici Cai , Jiangchun Gu , Sheqin Dong , Chung Kuan Cheng , Jun Gu, Corner block list: an effective and efficient topological representation of non-slicing floorplan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California

8

Yuliang Wu, Wenqi Huang, Siu-chung Lau, C.K. Wang and Gilbert H. Young, An Effective Quasi-Human Based Heuristic for Sloving Rectangle Packing Problem, in press.

9

Jon Louis Bentley, Multidimensional binary search trees used for associative searching, Communications of the ACM, v.18 n.9, p.509-517, Sept. 1975 [doi>10.1145/361002.361007]

CITED BY 2

Jun Yuan , Sheqin Dong , Xianlong Hong , Yuliang Wu, LFF algorithm for heterogeneous FPGA floorplanning, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China

Ou He , Sheqin Dong , Jinian Bian , Yuchun Ma , Xianlong Hong, An effective buffer planning algorithm for IP based fixed-outline SOC placement, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy

Robust low voltage low power analog mos VLSI design

ABSTRACT

Integrating analog, mixed signal and RF circuits with digital in a System-on-Chip (SoC) design solution is a major trend nowadays and finds many applications in areas like wireless and wireline communications and multimedia applications.This chapter presents statistical design techniques leading to optimization and yield enhancement of integrated CMOS analog and mixed signal solutions. In a SoC design, minimizing yield loss that often results from incorporating analog or RF parts in a large SoC digital design is becoming increasingly important to maintain a cost effective total solution. This is particularly true in today's deep sub-micron technologies where random process variations, supply noise and ground bounce become increasingly critical. Robust design techniques at both the schematic and physical layout levels will be discussed and demonstrated with design examples of low voltage CMOS analog integrated circuits.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Electronics communication Engineering

ELE 111 Introduction to Electronics Engineering

Relevance of Electronics Engineering curriculum to the practice of engineering in manufacturing and R&D environments. Various approaches and methods in problem solving. Introduction to, electronics and systems. Examples of applications.
ELE 211(E) Basics of Electrical Circuits

Physical electrical circuits. Modeling and measurements of currents and voltages in physical circuits. Definitions of charge, flux, power and energy and modeling their waveforms. Kirchoff's laws: Current and voltage equations. Circuit graphs. Graph matrices. Ideal 2- terminal and multi-terminal circuit elements: Linear and non-linear resistors, inductors and capacitors. Modeling of physical elements. Small-signal analysis. Solution of resistive circuits: Node voltage and mesh current methods. Circuit theorems: Tellegen's theorem. Superposition theorem. Reciprocity theorem. Thevenin and Norton theorems. Maximum power transfer theorem. Solution of dynamic circuits: Responses of first and second order dynamic circuits
ELE 222(E) Electronic Devices

Components and basic circuits: Operational amplifiers, concepts and application examples. Diodes: Terminal characteristics, analysis of diode circuits, semiconductor principles and structure of junction diode. DC biasing, BJT as an amplifier. MOSFET: Structure and operating modes.
ELE 242 Analysis of Circuits and Systems

State equations of higher order circuits and their solutions in t and s domain. State transition matrix. Zero state zero input responses. Stability, Routh criteria. Controllability and observability. Analysis of dynamical systems in W-domain. Sinusoidal steady state. Phasors, phasor network equations. Power and energy. Three phase systems. Network and system equations in s domain. Bode diagrams. Block diagram and signal flow graphs.
ELE 232 Signal Processing

Classification of signals and systems. Fourier analysis of continuous and discrete signals and systems. Modulation concept and sampling theorem. Sampling in time and frequency domain. Discrete and fast Fourier transforms. Transformation of continuous time systems into discrete time systems. Representation of difference eqations. State space equations and their solution. z transformation and their properties. Analysis of discrete time systems in z domain. Introduction to filtering.
TEL 212 Introduction to Electromagnetic Fields

Elementary electromagnetic field theory as summarized in Maxwell.s equations for time varying fields in integral and differential form, energy storage and quasistatic fields, EM field and materials, vector calculus and potential functions, time domain analysis of waves, PC assisted instruction of field calculations.
ELE 341 Analog Electronic Circuits

Multistage amplifiers. Operational amplifier circuits and applications. Circuits derived from op amps. Analog multipliers. Frequency response of amplifiers. Feedback, stability problems in feedback circuits, compensation. Sinusoidal oscillators. Power amplifiers.
ELE 321(E) Introduction to Digital Systems

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ELE 311 Introduction to Electronics Laboratory

* 1. Supply voltage circuits
* 2. DC characteristics of BJTs and MOSFETs
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ELE 322(E) Digital Electronic Circuits

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ELE 332 Network Synthesis

Network synthesis problem. Filter approximation: Butterworth and Chebyshev approximations, impedance and frequency normalization, Passive network synthesis: Positive real functions. Synthesis of LC, RC, RL, RLC networks: Cauer.s and Foster.s realizations. Synthesis of passive 2-ports, Positive real matrices, Synthesis of 2-ports converted to synthesis of 2-terminals. Ladder network synthesis: zero shifting technique. Active network synthesis: decomposition, coefficient matching and signal flow graph methods. Examples of active network synthesis using modern active devices (current conveyor, OTA, opamp)
ELE 352(E) Microprocessor Systems

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ELE 342 Telecommunication Engineering Basics

Amplitude modulation techniques. Amplitude modulators and demodulators. Frequency and phase modulation. Frequency modulators and demodulators. Frequency division multiplexing. Pulse modulation techniques. Quantization, compressing-expanding, analog-digital converters, delta modulation. Baseband data transmission. Intersymbol interference, Nyquist channel, multilevel baseband transmission, error performance analysis. Digital modulation techniques. Amplitude-shift, phase-shift and frequency-shift keying.
ELE 312 Analog Electronic Circuits Laboratory

* 1. Low-frequency power amplifiers
* 2. Analog integrated circuits building blocks
* 3. Frequency and pulse response of BJT amplifiers
* 4. Feedback and stability in transistorized amplifiers
* 5. Broad-band amplifiers
* 6. Low-frequency oscillators
* 7. Active filters
* 8. PLL applications

ELE 412 Semiconductor Devices

Constituents of semiconductor crystal. Poisson, current and continuity equations. Energy band diagrams. Thermal equilibrium. Injection level. Trapping. BJT in equilibrium. BJT under bias. High-bias effects in BJT. BJT dynamics. MOSFET structure. MOSFET under bias. Strong inversion and subthreshold models. Structural optimization of MOSFET. Secondary effects and MOSFET dynamics.
ELE 413 Very Large Scale Integrated Circuit Design I

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ELE 414 Microelectronic Analog Circuit Design

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ELE 415 Analog Integrated Circuits

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ELE 416 High Frequency Electronics

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ELE 417 RF Microelectronic Circuits

Introduction to RF and wireless technology. Modulation and detection. Multiple access techniques and wireless standards. Transceiver architecture. Low noise amplifiers and mixers. Oscillators. Power amplifiers.
ELE 418 RF Laboratory

* 1. s-parameters measurement setup
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ELE 419 Digital System Design

Adder circuits. The r's and (r-1)'s complement. Subtraction with r's and (r-1)'s complement. Realization of Boolean functions with multiplexers. ROM design with multiplexers. Design with Field Programmable Gate Arrays (FPGA). Register design. Algorithmic State Machine (ASM): ASM chart, control implementation, design with multiplexers and PLA's, some examples. State reduction in completely specified and incompletely specified sequential machines. State assignment in synchronous sequential circuits. Design of asynchronous circuits: Race-free state assignment. Asynchronous circuit design with Programmable Logic Controllers (PLC).
ELE 420 Artificial Neural Networks

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ELE 421 Introduction to Medical Electronics

The origin of the action potential, bioelectrical sources, and the main properties of bioelectrical signals. Origin and properties of other physiological parameters. Electroneurography, electrocardiography, electroencephalography, electromyography, electroretinography and evoked potentials. Other physiological measurements: blood pressure, blood volume, blood flow, heart sound, respiratory system measurements.
ELE 422 The Origin and Sensing Methods of Biological Signals

Introduction to human physiology: The cell and its function, origin of the action potential; bioreceptors; nervous, muscular, cardiovascular, respiratory, gastrointestinal, urinary and endocrin systems; the special sense organs; biological signals originated from human systems. Sensing and preprocessing of biological signals: Characteristics of biological signals, the basic amplifiers and basic circuits used for analog processing of biological signals, instrumentation amplifier; electrodes, features and applications; resistive, capacitive, inductive, piezoelectric, electromagnetic and termic transducers; transducer amplifiers and their calibration.
ELE 423 Modeling and Control of Biological Systems

Derivation of mathematical models of biological systems. Fundamental concepts; biological resistors and memories, models of neurons, signal analysis of biological systems and closed loop concept. Applications: The control loops of eye and sensing organs, the control of body temperature, the control of blood pressure, motion control loops
ELE 424 Ultrasound and Applications in Medicine

Basic features of ultrasound propagation: wave equation, characteristic impedance, diffraction, scattering, focusing, and Doppler effect, generation and detection of ultrasound, velocity and attenuation measurement techniques. Interaction of ultrasonic waves with tissue. Imaging methods: A and M mode imaging, static and dynamic (real time) imaging, three dimensional imaging, tissue characterization with ultrasound, biological effects of ultrasound, application of ultrasound in therapy
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Introducing of the CADENCE VLSI design environment. Examining the VLSI Design Flow. System level architectural design. Logic design and verification. Usage of VERILOG environment. Automatic synthesis of logic design. SYNOPSYS environment. Introduction of standard-cell libraries and their usage. Standard cell placement & routing. Full custom design strategies. Layout design in CADENCE - ARTIST design environment. Chip-level floorplanning and power distribution . VLSI test methods and design for testability.
ELE 426 Microelectronic Analog System Design

Types of analog filters and their frequency-response specifications. Active RC, Gm /C and SC filter configurations. Electrical and physical design of active filter circuits: Components, parasitics, on-chip tuning, noise and offset. Data converter design: DAC and ADC. Examples of integrated analog system design.
ELE 427 Microelectronics Technology

Brief history of the microelectronics technology. Planar technology. Micro-lithography. Thin films; Evaporation, sputtering and CVD techniques. Thermal oxidation of silicon. Doping techniques; diffusion, ion implantation and epitaxy. In process measurement and evaluation techniques. Process simulation; SUPREM. Process design; junction isolated bipolar IC and CMOS IC fabrication processes. Packaging. Yield analysis.
ELE 428 Industrial Electronics

Linear and nonlinear applications of operational amplifiers: Current sources, AC-DC converters, function generators, comparators, Schmitt trigger, oscillator applications. Analog building blocks: OTA applications, instrumentation amplifiers. PLL applications. Power Supplies: Design with linear regulator ICs, switched mode power supplies. Power MOSFET and its applications: Switching properties, safe-operation area, driver circuits, amplifiers, bridge operation. Sensors: temperature, moisture, pressure, displacement, light intensity sensors.
ELE 429 Communication Electronics Circuits

Communication System Blocks, Mixers; Diode, Active Mixers, balanced and unbalanced configurations and their applications, High Power RF Amplifiers; Class A, AB and B linear power amplifiers, high efficiency power amplifiers, design of Class D and E type amplifiers. Phase-Locked Loops (PLL) and their applications, Frequency synthesizers, Modulator and de- modulator circuits.
ELE 430 Radio-Television Systems

General receiver principles, superheterodyne receivers, selectivity, sensitivity, image frequency, receiver distortions, AM & FM broadcasting principles and systems, multiple carrier techniques and OFDM; PAL/SECAM/NTSC TV systems, PAL coding and decoding, picture artifacts, sampling and quantization of video signals, digital processing of video, video compression, MPEG, advanced TV systems, video recording, satellite and cable delivery of video signals.
ELE 431 Advanced Electronics Laboratory

IC building blocks: current and voltage sources, current and voltage references, amplifier stages, operational amplifier applications, operational transconductance amplifier (OTA) applications, current-conveyor applications, oscillator circuits, analog multiplier applications, IC characterization.
ELE 432 Microprocessor System Design

Software and hardware design of microprocessor-based systems and system components. Microprocessor peripherals; description and applications of parallel/serial communication interface units , integrated timer/counter circuits , memory elements , A/D and D/A converters, universal logic elements . Single-chip microcontrollers and multiprocessor digital systems. Realization of digital filters.
ELE 433 Digital Filters and Systems

Filtering by discrete (fast) Fourier transformation. Design aspects of digital filters and realization problem finite impulse filter design methods. Infinite impulse filter design, i) linear phase filters ii) windowing, iii) frequency sampling iv) optimal filter design methods. Infinite impulse response filter design : i) numerical integration methods ii) impulse invariance methods iii) bilateral z-transformation method. Filter design based on least-squares method. i) Pade method ii) FIR Wiener filter. System identification, inverse-filter design, prediction, signal processing applications using software realization State-space representation of discrete time systems. Observable, controllable, canonical representation. Controllability, observability, stability. Methods to design control systems. System design by state feedback (pole implementation) state observer design. Design of optimal control systems.
ELE 434 Nonlinear Circuits and Systems

Classification of algebraic and dynamic systems. State-space and input output representation of continuous and discrete time systems. State-space analysis stability of equilibrium points. Oscillators. Small signal analysis. Approximate analysis: Harmonic balance methods, numerical methods. Partitioning into linear dynamical and nonlinear algebraic subsystems. Input- output stability. Synthesis of nonlinear resistors and transfer functions. Design of algebraic systems as function approximation problem. Design of continuous and discrete-time dynamical systems: Synthesis of equilibrium points, design based on Lyapunov functions.
ELE 435 Engineering Systems Analysis

General look to engineering systems. Engineering systems other than electrical systems: mechanical, hydraulic, electro-mechanical and thermal systems. Application of disciplines developed for the analysis of the electrical circuits to these engineering systems. Existing ande the solutions of the system equations of these systems. Controbility and observability of the engineering systems. System components and modeling. Non-energical multiport components (transducer) and their advanced models
ELE 436 Digital System Design Laboratory

* 1. Characteristics of TTL and CMOS gates
* 2. Combinational circuit design
* 3. Flip-flops and triggering methods
* 4. Synchronous sequential circuit design
* 5. Using BUS in digital systems
* 6. Counters
* 7. Registers
* 8. Arithmetic operation units
* 9. Design of combinational logic circuits with programmable logic controller
* 10. Design of asynchronous sequential logic circuits with programmable logic controller

ELE 437 Biomedical Devices

Physiological effects of electricity and electrical safety. Microcomputers in medical instrumentation. Clinical measurement devices. Electrosurgical and physical therapy devices. Radiology and nuclear medicine devices. Computers in medicine. Computer axial tomography. Advanced topics in medical electronics.
ELE 438 Fundamentals of Medical Electronics Design

Design of high order active filters. Modeling and simulation of human cardiovascular system. The general principles in the design of microprocessor supported biomedical systems. The design of bioelectric signal processing systems: human reaction time measurement device, electrocardiography, arrhythmia detector, right leg driver, blood flow and heath rate measuring devices. Data compression techniques. Biotelemetry. Recording of biological signals to the magnetic recorders.
ELE 439 Therapeutic Medical Systems

Design of therapeutic medical equipment - basic concepts, definition and description of medical problems/conditions, physiology underlying the diseases/disabilities that can benefit from therapeutic devices and systems, applicable therapy techniques, design criteria for optimal benefit in a specific application, safety issues, effect of feedback control on system performance, open and closed loop feedback control, applicable transducers, exemplary applications in areas such as sensory problems (partial to total loss of vision, hearing, etc.), mobility problems, internal and external organ deficiencies, cardiovascular problems and cancer.
ELE 440 Computer Aided Devices in Medicine

Origins and properties of biological signals. Transducers for biological signals. Patient isolation methods. Fundamentals of computer units. Computer assisted biological signal acquisition, processing and monitoring. Archiving and transmitting of biological signals and images in and between medical centers. Computer aided telemetric system design. Microprocessor based blood pressure, body temperature, electrocardiogram, and electromyogram measurement devices.
ELE 441 Medical Electronics Laboratory

Some basic devices used for biological signal processing; electrocardiographic amplifier; transducers and electrodes; right leg driver; hydromechanical and electrical models of human cardiovascular system, digital processing of biological signals, adaptive and digital filters.
Sayfa Sorumlusu

asic design