Chip-Level Thermal Simulator to Predict VLSI Chip Temperature *

Chip-Level Thermal Simulator to Predict VLSI Chip Temperature *
Yi-Kan Cheng, and Sung-Mo Kang
Coordinated Science Laboratory
University of Illinois at Urbana-Champaign
Phone:(217) 244-0044 Fax:(217) 244-1946
yikanQuivlsi. csl.uiuc.edu
ABSTRACT
In this paper, a new thermal simulator is developed to
predict the steady-state and transient temperatures inside
a VLSI chip subjected to hea.ting by single or multiple
heat sources. It uses a mixed 3-D finite-difference
and 1-D analogous thermal circuit method, taking into
account any combination of boundary conditions, shape
of heat> sources, and packaging. An analytical method is
also presented and compared to the numerical method.
With this tool, the chip temperature can be predicted
accurately to provide design guidelines for VLSI module
placement and chip packaging.
I. INTRODUCTION
With downward scaling of device dimensions, the number
of gates on a single chip has been increasing steadily. The
increase in the chip size and power dissipation has lead
to an increase in the chip temperature. In fact, the temperature
of a packaged VLSI chip can vary by as many as
a few tens of degrees from the center to the edges of the
chip.
In the past, device and circuit-level thermal simulators
[l, 21 were developed to predict the device temperature as
a function of dissipated power or the temperature profile
of the whole integrated circuit. For small geometries, 1-
D a.nd 2-D simulations were adopted and the packaging
effects and the relative boundary conditions(BC's) were
usually simplified or even overlooked. In a VLSI chip,
however, these effects play important roles in determining
the temperature distribution over an entire chip.
The objective of this paper is to develop a chip-level
thermal simulator to accurately determine the temperature
distribution over a VLSI chip. The chip dimensions,
the shape and layout of heat sources, amount of dissipated
*This research was supported in part by Intel Corporation, Air
Force Rome Laboratory (F30602-94-1-0006), JSEP (N00014-94-Jpowers,
packaging materials, ambient temperatures, and
BC's can be specified by users. Based on this information,
a mixed 3-D finite-difference and 1-D equivalent thermal
circuit simulator calculates the temperature at every mesh
point. An analytical model is also implemented in this
simulator to calculate the temperat,ure of specific points
wit,h computational efficiency.
11. FORMULATION
The heat diffusion equation is the governing equation for
VLSI chip temperatures. For an isotropic material, the
general equation is written as [3]
(1)
-d+2T -d+2T -d+2T -g = _1 _dT
a 2 2 dy2 a z 2 IC at
subjected to the general BC:
where g is the power density of the source(s) (W/m3), k%
is the thermal conductivity (W/m '(2) of the bulk, Q is
the thermal diffusivity, h, is the heat transfer coefficient
(W/m2 "C), and n, is the outward direction normal to the
surface i. For steady-state case, the term will drop out.
Three kinds of BC's can be specified at the six surfaces
of the chip:
1. BC o f t h e first kind, also called isothermal BC. Temperature
is prescribed along the boundary surfaces
in this case and (2) will reduce to T = f2(z, y, z ) .
2. BC of the second kind. This is equivalent to prescribing
the magnitude of the heat flux along the
surfaces and (2) will reduce to = f i ( x , y, z ) . For
fi(z, y, z ) = 0, this is referred as insulated or adia-
1270) and Semiconductor Research Corporation(SRC93-DP-109). batac BC.
0-7803-2570-2/95 $4.00 01995 IEEE 1392
Authorized licensed use limited to: IEEE Xplore. Downloaded on December 12, 2008 at 05:10 from IEEE Xplore. Restrictions apply.
0.05 <
;70
Figure 1 : Simulated chip wiih mesh system.(not to scale)
,"Vl.,2 20)
Figure 2. Chip temperaturc profile with three rectangular
soiirces with dimension:(4~4),(2~44),(5~6l)o cated at
(28,28),(17,40) and (2,20) respectively. (unit: mesh point).
3. BC 01 the third kind. This is also called the convective
BC. The generd form this BC is exactly as
in (2). IIowever, a more physical form can be expressed
as the following:
where Ta is the ambient temperature.
A. Finite-Difference Model
Figure 1 illustrates the simplified model for the simulated
chip by finite-difference method. A 0.5cmx0.5cmx0.05cm
chip is divided, for example, to 50 x 50 x 25 meshpoints,
spccilied by users. Then the fiiiite-difference method is
iL,tivatcd once all the information has been inputted.
Tlie program uses Ihe c:ontrol volume finite-difference
approach [4] and the linear equations are solved using successiv?
over-relaxation algorithm(S0R). Several cases are
simulated as the foilowing. Figure 2 shows the temperature
distribution along the t,he X-Y surface at z 0.025cni
with several rectangular heat sources with different sizes,
different powers at different locations. The BC's are assumed
to be 50 "C all over the four sidewalls(isotherma1)
while insulated at the top and bottom surfaces. Tlie powers
are choseii t80 be 1.4W(source l), 0.4W(source 2) and
2.8W(source 3 ) . This figure reveals the 20 "C difference
from hot spots to the edge:j of the chip. This thermal
simulator can process any smooth heat, function and any
shape of heat sources, besides rectangular sources with
uniform power dissipation.
Figure
Fig. 2.
y-direclion x-dlreclon
Figure 4: 'Temperature profile with mixed BC's subjected to
three point sources al, (2,3),(30,45) and (70,20).
Transient simulation is also performed. An implicit
scheme 131 was used and the results are shown in Fig. 3.
From this figure we can conclude that it will take about
0.15ms for the chip to reach steady state at source 1, while
only take about 0.05ms at source 3.
Figure 4 shows the temperature distribution with 3
point sources subjected to mixed boundary conditions: top
and bottom surface are isothermal, back and right surfaces
are insulated, and the front, and left surfaces are convective
to ambient temperature 27 "c'. An equivalent contour
plot in Fig. 5 shows that the big temperature jump
around the heat source 1 c m have substantial effect on
any temperature-dependents chip or circuit behaviors.
R. Analytzcnl Model
An analytical niodel is also iml)lemcnt,ed in this simulator.
Analyt,ical melliod lins its limitation lor complex
Figure 5: Contour plot with mixed BC's subjectcd to three
point sources.
1393
Authorized licensed use limited to: IEEE Xplore. Downloaded on December 12, 2008 at 05:10 from IEEE Xplore. Restrictions apply.
Figure 6: Chip profile, including package, heat sink, and pins. Figure 7: Equivalent thermal circuit.
structures, however, it is more time efficient than numerical
methods whcn the temperatures need to be calculated
for only a few specific points. While the finite-difference
scheme requires information on all the neighboring meshpoints
to calculate the current mesh-point, the analytical
method needs not. For simplicity, only special case with
all six sides kept to zero temperature and with initial temperature
F ( z , y, z ) is presented here [3]:
m=l n=l p=l
K ( p m ,x ), K(vn,y ), i<(vpz, ) are kernels, (om,U, ! qP)a re
eigeiivaliies, F(pm, U,, vp) and ij(p,, v,, qp,t ') are transformed
pairs of F and power density g used in the integral
Transform [3, 51. For real computer implementation, only
finite terms are added. The number of terms used in this
series expansion is determined by the convergence criterion;
the additional terms which cont,ribute only a small
amount(0.01 "C) of change to this summation can be terminated.
To know the temperatures of one thousand out
of all 25000 meshed points, for example, the analytical
method took 10.72 seconds and finite-difference method
took 15.42 seconds CPU time on SUN SPARCstation 10
for the case in Fig. 2.
111. CHIPT EMPERATUWRITEH PACKAGING
It is essential to consider the packaging material and heat
sink in the thermal simulator since they are critical in
determining chip temperatures. Figure 6 shows the realistic
chip picture. This figure includes the bottom heat
sink, plastic or ceramic packaging materials around the
other bulk surfaces, and several pins. There are two more
BC's involved in a packaged chip. Firstly, the temperature
is continuous at the interface of two different materials,
i.e., T(')= 7"2).S econdly, the heat flux is continuous,
i.e., IC!''& an I = k i 2 ) e at interfaces. These extra BC's
could make this problem much more complicated, both
for finite-difference scheme and analytical method. In the
finite-difference scheme, it must take into account the different
thermal conductivities of two or three materials in
conjunction and then apply the above continuity properties.
In the analyt.ica1 method, there is no exact solutioii
of this chip structure. To solve this problem, a time efficient
heuristic method is used. Let us first look at the
chip structure in Fig. 6.
A. Packaged Chip Model for Worst Case Analysis
For the worst case analysis, we can assume the bottom
surface being convective to the ambient and the other five
surfaces adiabatic. This is a good approximation for a system
with small hi, (For example, free convectmionw ith the
air, hi only M 8W/m2 "C) a.nd the thermal conductivity
of the package is small compared to the heat sink. With
these underlying assumpt,ions, simulations can be done as
discussed in section 11.
B. Packaged Chzp Model in Realistic Case
If the above assumptions are removed, then the bottom
heat sink and the other five packaging materials are actually
all convective to the ambient 27 "C and a more
realistic model has to be built. Here we use the analogous
thermal czrcuzt concept for our package simulation,
as pictured in Fig. 7. This idea stems from that what the
t,emperature is to the heat flow is analogous to what the
voltage is to the the current flow. The relationship between
thermal and electric circuit is the following, where
p is the heat flow(TYatt).
mThermal Electriic After having this picture in mind, we now can look at
the thermal conduction problem as an electric one. There
are two kinds of the thermal resistance Ri in this picture:
(i)Rfk = K;Gck:geA, of a plane wall i, where Ai is the
area ,Li is the length of the plane wall, i.e., packages or
heat sink, and liiackagise the thermal conductivity of
the packaging material. (ii) Rth = from plane wall
1394
Authorized licensed use limited to: IEEE Xplore. Downloaded on December 12, 2008 at 05:10 from IEEE Xplore. Restrictions apply.
3' ,
Figure 8: 3-D temperature plot of thermal circuit model.
surfaces to tile air (or other fluid), where hi is the heat
t,ransfer coefscient, as in (2). T; in Fig. 7 is the ambient
temperature around the individual chip surface, i from 1
to 6. Here we have tacitly assumed that we can neglect
the lateral heat diRusion within the packages and the heat
sink so that the analogous i,hermal resistances can be put
in the 1-ID forrn perpendicular to the surfaces as in Fig. 7.
Once this is done, then the two resistances in series can be
added up and we may define a new term for convenience
as thc following:
(5)
where IT; is called overall heat frans,fer coeficzent. Therefore
t8he original complicat,ed packaged chip problem is
mapped to the simplified one by replacing hi's with Hi's.
Rotice that, however, the bulk of the chip still requires 3-
D simulation in stead of 1-11 or 2-U because the thickness
of'tlie hulk is not srnall enough to be ignored.
C. Simulation Resull
In Fig. 8 we show the simulated 3-D temperature profile
using the equivalent thermal circuit model in (5). Here
we assume that the thermal conductivity of the packaging
materialis 230 W/m OC(ceramic) and that ofthe heat sink
is 300 W/rn "C (gold), the thickness of the packages and
lieat sinks are all 0.5 mm. 'I'he lieat, sources are exactly the
same as in Fig. 2. This simulator required 27.90 seconds
CP1J time on SUN SPARCstation 10 for this ciise. We
also plot the lemperature. predicted by the worst case
model A and by the thermal circuit model B in Fig. 9 for
comparison.
Figure 9(a) shows that, the worst case analysis slightly
overestimates t,he chip tkniperature for srnall h; . However,
for t,he large hi ([or (example, 34700 W/m2 '6 for
forced convect,ion) as in Fg. 9(b), thc temperature difference
between model A and B can be as large as 2 'C'
at the boundaries of the chip. This is expected because
in reality, the small amount of heat transfer between the
chip and siirrounding ambient does OCCIII. And this difference
wiil increase as the heat transfer coeflicient increases.
Figure 9: Temperature distributions along the x-direction at
(y,z)=(25,5) (unitmesh point) with two different models and
two different hZ's.
Thus we expect the chip temperature to be lower llian in
tlhe worst case model prediction.
To take t,he effect of the pins into account, we can replace
kiackageii i above approximat,ely by
I& = + (1 - X)I<;aekagt (6)
where X=(Area of pins)/(Totai package area). This
means that we can handle the pins or any ot,her packaging
structures of a chip in our sirnulalor simply by using
equation (6).
117. CONCI,USIONS
Complete st,eady-st,ate and transient, teinperature simulator
has been developed to compute temperatures over an
entire chip. Diffprent boundary conditions, cllip layout,
shape of heat sources; power consumption, and pncltagiiig
parameters caii bc applied to this simulator. Mixed 3-D
finite-difference and 1-D equivalent t,liermal circuit siniulator
is used to estimate the packaged chip tcmpcraturc
efficiently. By usiiig t,his simulator. the VLSl chip t,em-
I be predict,ed t80 provide dcsigii guidcliiics for
module placement8 ai I (1 chip packaging .
REFER EN c: E s
[l] V. Ilwycr, A. Franklin, and D. Campbell, '"lherinal
failure ir: semiconductor devices," Solid State Electrmzcs,
~01.33p,p . 553-560, Maj. 1990.
[a] K. Fukahori, P. Gray, "Coiiiput~ers irnulat~iono f iiitegrated
circuits iii t,hc presence of electrothermal illteract,
ion," IBEE J. ,i'O/id-,StGtc C i r c ~ i ip~p,. 834-846,
Dec. 1976.
[3] M.N. 07,isik)H ourLda,ry vah~P roblems of H c a t C'oiaduction.
London, U.K. :Oxford, 1963.
[4] M.N. Ozisik, I k i t e DzjJerencc Xethods in Hcat
Transfer. CRC Press, 1994.
[5] R.V. Churchill, J.W. Brown, Pourier S'crzes a n d
Boundary Vukiie Problems. 4th ed. McCrnw-Hill,
1987.
1395
Authorized licensed use limited to: IEEE Xplore. Downloaded on December 12, 2008 at 05:10 from IEEE Xplore. Restrictions apply.